Robert J. Bowman

A Low Power, Scalable, DAC Architecture for Liquid Crystal Display Drivers

The proliferation of portable electronic products such as cellular telephones and personal digital assistants has created a high demand for small format liquid crystal displays (LCD) with increasing bit resolution. The electronic drivers for these display applications must adhere to stringent power and area budgets. This paper describes a low-power, area efficient, scalable, digital-analog conversion (DAC) integrated circuit architecture optimized for driving small format LCDs. A 12 channel, 9-bit DAC driver based on this architecture, implemented in 0.5 mum CMOS technology and suitable for 1/4 VGA resolution displays, exhibited a 2 MSPS conversion rate, 252 muW power dissipation per channel using a 5 V supply, and a per DAC die area of 0.042 mm2. This performance sets a new standard for DAC display drivers in joules per bit areal density at less than 0.58 pJ per bit per mm2 .

Single Fermi Level Thin-Film CMOS on Glass: The Behavior of Enhancement-Mode PMOSFETs From Cutoff Through Accumulation

A device model which describes the behavior of thin-film transistors fabricated in crystalline silicon on glass is introduced. The dc current-voltage characteristics of fully depleted thin-film silicon p-channel enhancement-mode MOSFETs operated in accumulation is provided. Physically derived expressions are presented for drain current in the accumulation and depletion regions which include the correct dependence on drain voltage, film thickness, and doping level. AC-infin model is realized from cutoff to accumulation by using an interpolant around the flatband voltage and a hyperbolic tangent blending function. The device model shows excellent agreement with measured results for output, transfer, and transconductance characteristics. A compact circuit simulation model has also been implemented in the Spectre circuit simulator using Verilog-A.

An educational program for engineering careers in analog and mixed-signal electronic design

The analog and mixed-signal (AMX) BS/MS dual degree program in electrical engineering at RIT introduces the student to a broad range of subject material considered essential for a career in analog circuit design. It emphasizes the actual design and fabrication of complex analog and mixed-signal integrated circuits. Digital and analog signal processing principles are presented in a coordinated design environment. This paper outlines logical objectives of an educational program for analog and mixed-signal engineering, describes the AMX program that was launched in the Fall 2004, and discusses planned improvements.

Inspiring electrical engineering students through fully-engaged hands-on learning

Hands-on learning has proven to be very effective in motivating electrical engineering students to study foundation courses. The advent of student-owned, functionally robust, portable test and measurement equipment, now offers fertile ground for developing innovative pedagogy to more fully engage and inspire students. In this paper we discuss two examples of how student-owned test and measurement instrumentation is impacting the electrical engineering curriculum at RIT: in a Freshman Practicum course with a flipped lab and in a Certificate Program in Mechatronics to enable the required laboratory content to be delivered online.

Fringing Field Effects in Thin-Film Silicon Transistors on Glass

A new process enabling the transfer of a single-crystal silicon film to a glass substrate has been developed allowing for the creation of fully crystalline thin-film silicon-on-glass (SiOG) transistors. The dominant 2-D effect in SiOG transistors results from fringing electric field lines emanating through the glass substrate between the source, drain, and thin-film channel regions. The fringing field leads to a shift in the flatband or threshold voltage in a similar manner to drain-induced barrier lowering. The fringing field effect can lead to an 11% shift in flatband for devices with channel length of 4 μm and a nominal flatband of -1 V. A compact model for the fringing field in these devices has been developed using conformal mapping techniques that capture the dependence on both channel length and the relative size of the source and drain electrodes. The model accurately predicts the influence of the fringing field on subthreshold drain current for SiOG PFETs operating in accumulation. The model is validated against the 2-D device simulator Silvaco Atlas.