Robert J. Simcoe

Algorithms for providing bandwidth and delay guarantees in input-buffered crossbars with speedup

Investigates some issues related to providing QoS guarantees in input-buffered crossbars with speedup. We show that a speedup of 4 is sufficient to ensure 100% asymptotic throughput with any maximal matching algorithm employed by the arbiter. We present several algorithms which ensure different delay guarantees with a range of speedup values between 2 and 6. We demonstrate that with relatively simple arbitration algorithms and a speedup that is independent of the switch size, it is possible to ensure delay guarantees which are comparable to those available for output-buffered switches.

Reliable and efficient hop-by-hop flow control

Hop-by-hop flow control can be used to fairly share the bandwidth of a network among competing flows. No data is lost even in overload conditions; yet each flow gets access to the maximum throughput when the network is lightly loaded. However, some schemes for hop-by-hop flow control require too much memory; some of them are not resilient to errors. We propose a scheme for making hop-by-hop flow control resilient and show that it has advantages over schemes proposed by Kung. We also describe a novel method for sharing the available buffers among the flows on a link; our scheme allows us to potentially reduce the memory requirement (or increase the number of flows that can be supported) by an order of magnitude. Most of the work is described in the context of an ATM network that uses credit based flow control. However our ideas extend to networks in which flows can be distinguished, and to rate based flow control schemes.

On the speedup required for work-conserving crossbar switches

Describes the architecture for a work-conserving server using a combined input-output buffered crossbar switch. The switch employs a novel algorithm based on output occupancy-the Lowest-Occupancy-Output-First Algorithm (LOOFA)-and a speedup of only 2. A work-conserving switch provides the same throughput performance as an output buffered switch. The work-conserving property of the switch is independent of the switch size and input traffic pattern. We also present a suite of algorithms that can be used in combination with LOOFA. These algorithms determine the fairness and delay properties of the switch. We also describe a mechanism to provide delay bounds for real-time traffic using LOOFA. These delay bounds are achievable without requiring output buffered switch emulation.

Perspectives on ATM switch architecture and the influence of traffic pattern assumptions on switch design

Switch designs and the uniform distribution traffic pattern that has been the basis of much switch design analysis are discussed. In particular it is shown that head of line blocking is not the major cause of switch and link underutilization. Switch fabric and buffer system input bandwidth tradeoffs are described. For client server applications it is shown that having the majority of switch buffers on the input side of a switch reduces overall switch buffering.