Robert K. Leidy

A Novel Approach to Photonic Packaging Leveraging Existing High-Throughput Microelectronic Facilities

Silicon photonics leverages microelectronic fabrication facilities to achieve photonic circuits of unprecedented complexity and cost efficiency. This efficiency does not yet translate to optical packaging, however, which has not evolved substantially from legacy devices. To reach the potential of silicon photonics, we argue that disruptive advances in the packaging cost, scalability in the optical port count, and scalability in the manufacturing volume are required. To attain these, we establish a novel photonic packaging direction based on leveraging existing microelectronics packaging facilities. We demonstrate two approaches to fiber-to-chip interfacing and one to hybrid photonic integration involving direct flip-chip assembly of photonic dies. Self-alignment is used throughout to compensate for insufficient placement accuracy of high-throughput pick and place tools. We show a self-aligned peak transmission of -1.3 dB from standard cleaved fibers to chip and of -1.1 dB from chip to chip. The demonstrated approaches are meant to be universal by simultaneously allowing wide spectral bandwidth for coarse wavelength division multiplexing and large optical-port count.

Practicing the top antireflector process

Thickness variations in photoresist caused by substrate topography, and normal variations in deposited thin films, arc unavoidable sources of linewidth variation in optical lithography. Thin film interference effects cause exposure to vary by large amounts. A new approach to controlling these effects is the use of a top antircficctor (TAR) film on top of the photoresist. In this paper, the performance of a process using a water soluble TAR material is described. Simulation and experimental results arc given which show the effectiveness in controlling wafer reflectivity, and exposure dose in the presence of varying insulator and resist films. The effect of the TAR process on focus and exposure latitude is examined and initial results from device manufacturing are presented.

When is bilayer thin-film imaging suitable: comparison with single-layer resists

Silicon-containing bilayer thin-film imaging resists versus single layer resists for a variety of different mask types, from both a focus-expose window, etch selectivity, and process integration perspective are examined. Comparable lithographic performance is found for 248 nm single layer and bilayer resists for several mask levels including: a 135 nm dense contact/deep trench mask level, a 150 and 125 nm equal line space mask printed over trench topography, and dual damascene mask levels with both vias and line levels. The bilayer scheme is shown to significantly relax the dielectric to resist etch selectivity constraint for the case of a dense contact or trench hardmask level, where high aspect ratio dielectric features are required. Only a bilayer resist scheme in combination with a transfer etch process enables the line/space pattern transfer from the imaging layer to the bottom of a trench with a combined aspect ratio > 10. When the single layer resist depth of focus window is limited by both the topography and variations in the underlying dielectric stack thickness, as is the case for the dual damascene via and line levels, bilayer resist is shown to be a practical alternative.

Photonic packaging in high-throughput microelectronic assembly lines for cost-efficiency and scalability

We demonstrate silicon photonic packaging that can be fully exercised in existing microelectronic packaging facilities. We show low optical loss and point towards notably improved assembly cost and scalability in both volume and optical port-count.

Breaking the mold of photonic packaging

The packaging of photonic devices remains a hindering challenge to the deployment of integrated photonic modules. This is never as true as for silicon photonic modules where the cost efficiency and scalability of chip fabrication in microelectronic production facilities is far ahead of current photonic packaging technology. More often than not, photonic modules are still packaged today with legacy manual processes and high-precision active alignment. Automation of these manual processes can provide gains in yield and scalability. Thus, specialized automated equipment has been developed for photonic packaging, is now commercially available, and is providing an incremental improvement in cost and scalability. However, to bring the cost and scalability of photonic packaging on par with silicon chip fabrication, we feel a more disruptive approach is required. Hence, in recent years, we have developed photonic packaging in standard, highthroughput microelectronic packaging facilities. This approach relies on the concepts already responsible for the attractiveness of silicon photonic chip fabrication: (1) moving complexity from die-level packaging processes to waferlevel planar fabrication, and (2) leveraging the scale of existing microelectronic facilities for photonic fabrication. We have demonstrated such direction with peak coupling performance of 1.3 dB from standard cleaved fiber to chip and 1.1 dB from chip to chip.

SiGe HBTs in 90nm BiCMOS technology demonstrating 300GHz/420GHz f T /f MAX through reduced R b and C cb parasitics

Scaling both the fT and the fMAX of SiGe HBTs is quite challenging due to the opposing physical device requirements for improving these figures of merit. In this paper, millisecond anneal techniques, low temperature silicide and low temperature contact processes are shown to be effective in reducing the base resistance. These processes when combined with a novel approach to address the collector-base capacitance are shown to produce high performance SiGe HBT devices which demonstrate operating frequencies of 300/420GHz fT/fMAX. This is the first report of 90nm SiGe BICMOS with an fMAX exceeding 400GHz.

Comparing photomask and wafer post-develop defect formation

The reduction of post-develop defects in photomask making is significantly more critical than in wafer processing. While wafers can afford to experience some level of defect density, photomasks are required to be defect free. Defect density learning in photomask making is expensive and time-consuming given the material and exposure time costs. In a wafer fab, it is much easier to run factorial experiments to get large amounts of data in a short amount of time. Some photomask making and wafer processing defect generation mechanisms are the same. Here a study of the formation of resist material residues during develop will be compared between photomask and wafer processing. Wafer processing experience will provide insight into photomask post-develop defect formation. Several options for the elimination of this defect type will be discussed. Differences in implementation strategies between photomask makers and wafer lithographers will also be discussed.