Robert Mcilhenny

On the implementation of a three-operand multiplier

A new approach for a three-operand multiplier is proposed, using initial two-level radix-4 recoding, in order to reduce the cost and delay of other utilized methods. A three-operand 4-bit multiplier is demonstrated as a model, and serves as a building block for three-operand multipliers of higher precision. The proposed method is shown to yield a significant reduction in both the cost and delay of a three-operand 4-bit multiplier.

On-line algorithms for complex number arithmetic

A class of on-line algorithms for complex number arithmetic is presented These algorithms adopt a redundant complex number system (RCNS) to represent complex numbers as a single number. Such a scheme simplifies the specification of the design, and has the additional effect that single precision complex arithmetic can be easily reconfigured for double-precision real arithmetic. We present cost/spl times/delay comparisons with the more conventional approach to show a significant improvement, demonstrating that the presented algorithms are attractive for VLSI systems demanding complex number operations.

Design and FPGA implementation of radix-10 algorithm for square root with limited precision primitives

We present a radix-10 fixed-point digit-recurrence algorithm for square root using limited-precision multipliers, adders, and table-lookups. The algorithm, except in the initialization steps, uses the digit-recurrence algorithm for division with limited-precision primitives. We discuss the proposed square root algorithm, a design, and its FPGA implementation on a Xilinx Virtex-5 FPGA. We present the cost and delay characteristics for precisions of 7 (single-precision), 8, 14 (double-precision), 16, 24, and 32 decimal digits. The costs range from 720 to 2263 LUTs with maximum clock frequencies around 53MHz, and latencies ranging from 133 to 597 ns (with unoptimized routing delays). The proposed scheme uses short (2–3 digit-wide) operators which leads to compact modules, and may have an advantage at the layout level as well as in power optimization. The proposed approach is general and can be adapted to other higher radix square root implementations. Moreover, a combined scheme for division and square root can be efficiently implemented.

Design and FPGA implementation of radix-10 combined division/square root algorithm with limited precision primitives

A combined decimal division/square root scheme using limited-precision multipliers, adders, and table-lookups is presented. The combined algorithm, except in the initialization steps, uses a slightly modified digit-recurrence algorithm for division with limited-precision primitives. We describe the proposed combined division/square root algorithm, a design, and its FPGA implementation on a Xilinx Virtex-6 FPGA. We present the cost and delay characteristics for precisions of 7 (single-precision), 8, 14 (double-precision), 16, 24, and 32 decimal digits. The costs range from 1384 to 4066 LUTs with maximum clock frequencies around 68MHz, and latencies ranging from 102 to 485 ns (with unoptimized routing delays). The proposed scheme uses short (2 to 4 digit-wide) operators which leads to compact modules, and may have an advantage at the layout level as well as in power optimization. The proposed approach is general and can be adapted to other higher radix combined division/square root implementations.

BigSky - an on-line arithmetic design tool for FPGAs

We present a project to design, implement and use online arithmetic (M.D. Ercegovac and T. Lang, 1988) modules for reconfigurable hardware suitable for signal processing tasks. The project involves: (i) design, implementation and evaluation of a library of parameterized macros for primitive and composite/variable precision arithmetic (Underground); (ii) development of a high-level design environment for facilitating design of FPGA-oriented arithmetic-intensive structures (BigSky); and (iii) experiments with the system.

On the design of a radix-10 online floating-point multiplier

This paper describes an approach to design and implement a radix-10 online floating-point multiplier. An online approach is considered because it offers computational flexibility not available with conventional arithmetic. The design was coded in VHDL and compiled, synthesized, and mapped onto a Virtex 5 FPGA to measure cost in terms of LUTs (look-up-tables) as well as the cycle time and total latency. The routing delay which was not optimized is the major component in the cycle time. For a rough estimate of the cost/latency characteristics, our design was compared to a standard radix-2 floating-point multiplier of equivalent precision. The results demonstrate that even an unoptimized radix-10 online design is an attractive implementation alternative for FPGA floating-point multiplication.

On the design of an on-line FFT network for FPGA's

In this paper a novel implementation is presented for an on-line FFT network, using complex on-line arithmetic, based on adopting a redundant complex number system (RCNS) to represent complex operands as a single number. We present cost comparisons with alternative approaches, to demonstrate a significant improvement in design for FPGAs.

On using 1-out-of-n codes for (p,q) counter implementations

A new approach for implementing (p,q) counters is introduced, using 1-out-of-n code modules. The circuits were implemented in 1.2 /spl mu/m CMOS technology, and simulated using HSpice to measure the cost, delay, and average power consumption. Through simulation, the new method is shown to yield an average 19% reduction in critical delay, and an average 30% reduction in average power consumption, with the tradeoff of a 38% increase in average cost.

On the design of an on-line complex FIR filter

In this paper, we present a novel implementation for an N-tap complex finite impulse response (FIR) filter, using complex number on-line arithmetic, based on adopting a redundant complex number system (RCNS) to represent complex operands as a single number. We present cost comparisons with (i) a real number on-line arithmetic approach and (ii) a real number parallel arithmetic approach, to demonstrate a significant improvement in cost.

BigSky-a tool for mapping numerically intensive computations onto reconfigurable hardware

In this paper we present a software tool for designing and implementing numerically intensive computations onto reconfigurable hardware. The design utilizes on-line arithmetic modules to achieve efficient performance on FPGA structures. This tool facilitates the design for a variety of signal processing tasks demanding low cost and high throughput.