Publication


Featured researches published by Robert T. Golla.


Archive | 2009

Throughput-Oriented Multicore Processors

James Laudon; Robert T. Golla; Greg Grohoski

Many important commercial server applications are throughput-oriented. Chip multiprocessors (CMPs) are ideally suited to handle these workloads, as the multiple processors on the chip can independently service incoming requests. To date, most CMPs have been built using a small number of high-performance superscalar processor cores. However, the majority of commercial applications exhibit high cache miss rates, larger memory footprints, and low instruction-level parallelism, which leads to poor utilization on these CMPs. An alternative approach is to build a throughput-oriented, multithreaded CMP from a much larger number of simpler processor cores. This chapter explores the tradeoffs involved in building such a simple-core CMP. Two case studies, the Niagara and Niagara 2 CMPs from Sun Microsystems, are used to illustrate how simple-core CMPs are built in practice and how they compare to CMPs built from more traditional high-performance superscalar processor cores. The case studies show that simple-core CMPs can have a significant performance/watt advantage over complex-core CMPs.


asian solid state circuits conference | 2007

UltraSPARC T2: A highly-treaded, power-efficient, SPARC SOC

M. Shah; J. Barren; J. Brooks; Robert T. Golla; G. Grohoski; Nils Gura; R. Hetherington; P. Jordan; M. Luttrell; C. Olson; B. Sana; Denis Sheahan; Lawrence Spracklen; A. Wynn


Archive | 2004

Apparatus and method for fine-grained multithreading in a multipipelined processor core

Ricky C. Hetherington; Gregory F. Grohoski; Robert T. Golla


Archive | 2004

Fetch speculation in a multithreaded processor

Jama I. Barreh; Robert T. Golla


Archive | 2004

Method and appratus for power throttling in a multi-thread processor

Robert T. Golla; Ricky C. Hetherington


Archive | 2004

Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor

Jeffrey S. Brooks; Christopher H. Olson; Robert T. Golla


Archive | 2004

Efficient utilization of a store buffer using counters

Robert T. Golla; Mark A. Luttrell


Archive | 2003

Method and apparatus to limit register file read ports in an out-of-order, multi-stranded processor

Robert T. Golla; Chandra M. R. Thimmannagari; Sorin Iacobovici; Rabin A. Sugumar; Robert Nuckolls


Archive | 2009

PHYSICALLY-INDEXED LOGICAL MAP TABLE

Robert T. Golla; Jama I. Barreh; Howard L. Levy


Archive | 2004

Thread-based clock enabling in a multi-threaded processor

Robert T. Golla; Jeffrey S. Brooks; Christopher H. Olson

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