Robert Vermot-Gauchy

Voice-excited predictive coder (VEPC) implementation on a high-performance signal processor

In this paper, we discuss the implementation of a medium-bit-rate linear prediction baseband coder on an IBM bipolar signal processor prototype having a high processing capacity. We show that the implementation of our algorithm requires a processing load of 5 MIPS, with a program size of 5K instructions. We then discuss the application of our coder in a normal telephone environment, which requires mu-law to linear PCM conversion and other signal processing functions such as voice activity detection, automatic gain control, echo control, and error recovery. Quality evaluation tests are also reported which show that this type of coder, operating at 7.2 kbps, allows the transmission of telephone speech with communications quality. Moreover, obtained intelligibility scores and speaker recognition levels are high enough to demonstrate that this coder is a good candidate for telephony applications such as digital trunk transmissions, satellite speech communications, secure voice communications, and audio distribution systems.

Voice excited predictive coder (VEPC) implementation on 10 MIPS signal processor

In this paper, we discuss the Implementation of a low bit-rate linear prediction base-band coder on a bipolar signal processor having a processing capacity of 10 millions of instructions per second (MIPS). We show that the implementation of our algorithm requires less than 5 MIPS, with a ROS occupancy less than 5 K instructions. Some quality evaluation tests are also reported, and show that this type of coder operating at 7.2 kbps, provides a good communications quality, an intelligibility which is sufficient for most of telephony applications, and a perfect speaker recognition (natural voice).