Robert W. Bower

Growth Kinetics Observed in the Formation of Metal Silicides on Silicon

Backscattering of MeV He ions has been used to investigate the composition and growth kinetics of metal silicides formed from thin films of Pd, Ti, Cr, and Mo evaporated onto Si. In each system studied, one silicide phase predominated (Pd2Si, TiSi2, CrSi2, and MoSi2). The thickness of the phase increased with (time)0.5 for Pd2Si and TiSi2, and linearly in time for CrSi2 and MoSi2. It was found that these two time dependencies correlate directly with the reaction sensitivity to a thin oxide interface (<100 A) and to the extent of the silicide formation in the neighborhood of a typical device contact region.

Characteristics of aluminum‐titanium electrical contacts on silicon

An aluminum‐titanium metallization scheme for use in silicon integrated circuits is described. This metallization can produce high‐conductance electrical contacts with negligible dissolutions of silicon. The desirable contact is lost, however, if a TiAl3 reaction product is allowed to consume the entire Ti layer. The TiAl3 forms during the postmetallization heat treatment used to stabilize the electrical characteristics of the contact. The Ti layer is found to be consumed in this reaction at a rate proportional to t1/2, where the rate constant is determined to be d=d0 exp(−Ea/kT), where d0 ≈ 0.15 cm2/sec and Ea ≈ 1.85 eV. This rate constant can be used to determine the thickness of titanium layer necessary to produce the desirable electrical contact.

Low temperature Si3N4 direct bonding

Extremely strong bonds can be formed between smooth, clean layers of Si3N4 at temperatures ranging between 90 and 300 °C. These bonds have been formed between Si3N4 layers deposited on various substrates with deposition temperatures as low as 300 °C. The bond is initially formed at room temperature and subsequently annealed at temperatures ranging between 90 and 300 °C. Thus, the materials bonded in this manner are never exposed to temperatures higher than 300 °C. This low temperature bond greatly expands the range of applications of direct bonding which had heretofore been restricted by the temperatures of 700 to 1000 °C required by conventional wafer bonding.

MOS field effect transistors formed by gate masked ion implantation

MOS enhancement mode field effect transistors with a circular geometry and with drains offset from the gate by distances from 0.1 mil to 0.9 mil were implanted with boron ions to fill in the offset region and thus achieve perfect alignment (i.e., no overlap) between gate and drain. The energies used were 50 to 100 keV and a 4000 A-thick aluminum gate acted as a mask to prevent ions from penetrating into the channel region. The best junctions were obtained with 100-keV ions, with the sheet resistances being typically 4000 ω/□ for the implanted region. This additional drain resistance was quite small compared to the channel resistance of the devices and so was not objectionable. Ordinary diffused MOSFETs were included on the same wafers for comparison with the ion implanted MOSFETs. It was found that the differences in noise, leakage, and drain breakdown voltage were not serious. The chief advantage of the ion implanted MOSFET is the extremely low feedback capacitance due to the lack of gate-drain overlap, but this advantage is difficult to exploit in a conventional package because of the package capacitance. However, a significant difference was noted in switching characteristics between diffused and ion implanted MOSFETs mounted on TO-18 headers.

Surface Roughness of Hydrogen Ion Cut Low Temperature Bonded Thin Film Layers

We have observed that wafer splitting from hydrogen ion implantation into silicon after low temperature direct bonding creates an expunged film with a surface roughness that is ~1 nm (RMS). This result is an order of magnitude smoother than the previous work (~10 nm RMS). The key improvement is the use of low temperature bond in our work resulting in a strong bond far below the cut temperature. The smooth as-split surfaces produced using a low temperature bond are very important for creation of very thin (<50 nm) silicon-on-insulator (SOI), three-dimensional bonded structures and nanostructures that are split after processing.

Aligned wafer bonding: a key to three dimensional microstructures

Successful fabrication of critically aligned three dimensional structures has been achieved by combining precision alignment procedures and techniques for direct silicon bonding. This produces three dimensional bonded layers that might include combinations of mechanical, electronic and/or optical elements formed in separate prefabricated layers. We call this techniquealigned wafer bonding. The precise aligned bonding of the features was done with an Optical AssociatesHyperline 400 Infrared Aligner. This machine can hold two imprinted wafers face to face while projecting an infrared image of the surfaces to a viewing screen. An array of alignment marks were etched into the surface of silicon wafers with hot potassium hydroxide. These V-grooves were then precisely aligned and the wafers were brought into contact for initial bonding. Subsequent high temperature annealing was used to strengthen and complete the chemical bonding. The instrumentation used in this work required alignment features with a vertical dimension of 30 micrometers to produce a suitable infrared image. We found that the apparent size of the images produced by the optical system limited the accuracy in precision alignment. However, with reduced wafer separation, we achieved wafer alignment with an accuracy of better than 5 micrometers. This technique would generally be used for the precision alignment and bonding of complementary micromechanical, electrical, or optical structures during the formation of three dimensional devices. The details of the aligned wafer bonding and its applications are presented.

The influence of boron ion implantation on hydrogen blister formation in n-type silicon

We have studied the formation of surface blisters in 〈100〉 n-type silicon following co-implantation with boron and hydrogen. The silicon substrates had four different n-type dopant levels, ranging from 1014 to 1019 cm−3. These substrates were implanted with 240 keV B+ ions to a dose of 1015 cm−2, followed by a rapid thermal anneal at 900 °C for 30–60 s to force the boron atoms into substitutional lattice positions (activation). The samples were then implanted with 40 keV H+ to a dose of 5×1016 cm−2. The implanted H+ distribution peaks at a depth of about 475 nm, whereas the distribution in the implanted B+ is broader and peaks at about 705 nm. To evaluate the role of the B+ implantation, control samples were prepared by implanting with H+ only. Following the H+ implantation, all the samples were vacuum annealed at 390 °C for 10 min. Blisters resulting from subsurface cracking at depths of about 400 nm, were observed in most of the B+ implanted samples, but not in the samples implanted with H+ only. This s...

The design and fabrication of a magnetically actuated micromachined flow valve

Abstract In this paper, a magnetically actuated valve, manufactured by silicon and thin-film micromachining, is considered. An analysis of the magnetic circuit is made to determine the critical design parameters, and a fabrication sequence is described. An integrated array of these microvalves, when combined with chemical microsensors, is intended to form the basis of an automated flow distribution and chemical analysis system. The feasibility of magnetic actuation, an addressing scheme, and the fabrication process are discussed.

Insulated gate field effect transistors fabricated using the gate as source-drain mask

Conventional construction of an IGFET involves diffusing the source-drain junctions, then placing the gate over the channel area. To insure modulation of the entire channel area the gate must overlap the source and drain by an amount required by mask alignment tolerance. This overlap adds undesirable parasitic capacitance from source to gate and drain to gate. In this paper, two methods of forming the source-drain junction using the gate itself as the channel mask are described. These methods eliminate the gate alignment problem and therefore simplify fabrication and greatly reduce the parasitic gate capacitance. The first method uses ion implantation to form the source drain junctions. The metal gate structure is fabricated prior to the formation of the source and drain. The metal gate then acts as a mask against implantation doping in the channel region. Furthermore, the source and drain junctions are automatically placed for minimum gate to source-drain overlap. This technique is applicable to ion implantation because of the low temperature nature of this doping process. If a polycrystalline silicon film replaces the metal gate, conventional diffusion technique can be applied to this technique. Comparable structures were fabricated using conventional techniques and both of-the methods described here. The characteristics of each of these devices will be discussed.

DEEP (1–10 μ) PENETRATION OF ION‐IMPLANTED DONORS IN SILICON

Deep penetration of donors has been observed as a result of 20‐kV Sb ion implantations into 〈110〉‐ and 〈111〉‐oriented, high‐resistivity silicon. The density profiles were measured by a capacitance‐voltage method. The deep penetrating tail was found to be independent of such experimental parameters as temperature of implant (for T ≥ 300°C), orientation, annealing, and surface condition; and to empirically follow a N ∝ (x + B)2.2 dependence over four orders of magnitude (B ≈ 0.15 μ). This component has not been observed previously in silicon and has a different dependence on implantation parameters and a different functional form than that observed in ion channeling.