Robert Yung

Design decisions influencing the UltraSPARC's instruction fetch architecture

Designing a modern microprocessor is a complex task that demands careful balance between cycle time, cycle-per-instruction and area costs. In particular, the instruction fetch unit greatly affects the performance of a multi-issue processor. It must provide adequate bandwidth to sustain peak instruction issue rate and must predict future instruction sequences with high accuracy. In the UltraSPARC prefetch and dispatch unit design, we examined a technique that combined two prediction methods: predictive set-associative cache and in-cache prediction. This combination was compared with alternative designs such as direct-mapped and set-associative caches, and a branch history table and a branch target buffer. We chose the combined prediction technique for its fast cycle time, lower cycle-per-instruction, and lower area costs. This paper summarizes the trade-off decisions made in the design of the UltraSPARC instruction prefetch and dispatch unit.