Roberto Zafalon

Analyzing on-chip communication in a MPSoC environment

This work focuses on communication architecture analysis for multi-processor systems-on-chips (MPSoCs), and it leverages a SystemC-based platform to simulate a complete multi-processor system at the cycle-accurate and signal-accurate level. These features allow to stimulate the communication sub-system with functional traffic generated by real applications running on top of a configurable number of ARM processors. This opens up the possibility for communication infrastructure exploration and for the investigation of its impact on system performance at the highest level of accuracy. Our simulation environment proved capable of a detailed comparative analysis between two industry-standard communication architectures, under realistic workloads and different system configurations, pointing out the impact of fine grained architectural mismatches on macroscopic performance differences.

MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures

Technology trends enable the integration of many processor cores in a System-on-Chip (SoC). In these complex architectures, several architectural parameters can be tuned to find the best trade-off in terms of multiple metrics such as energy and delay. The main goal of the MULTICUBE project consists of the definition of an automatic Design Space Exploration framework to support the design of next generation many-core architectures.

Energy estimation and optimization of embedded VLIW processors based on instruction clustering

Aim of this paper is to propose a methodology for the definition of an instruction-level energy estimation framework for VLIW (Very Long Instruction Word) processors. The power modeling methodology is the key issue to define an effective energy-aware software optimisation strategy for state-of-the-art ILP (Instruction Level Parallelism) processors. The methodology is based on an energy model for VLIW processors that exploits instruction clustering to achieve an efficient and fine grained energy estimation. The approach aims at reducing the complexity of the characterization problem for VLIW processors from exponential, with respect to the number of parallel operations in the same very long instruction, to quadratic, with respect to the number of instruction clusters. Furthermore, the paper proposes a spatial scheduling algorithm based on a low-power reordering of the parallel operations within the same long instruction. Experimental results have been carried out on the Lx processor, a 4-issue VLIW core jointly designed by HPLabs and STMicroelectronics. The results have shown an average error of 1.9% between the cluster-based estimation model and the reference design, with a standard deviation of 5.8%. For the Lx architecture, the spatial instruction scheduling algorithm provides an average energy saving of 12%.

Low-power data forwarding for VLIW embedded architectures

Proposes a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, which provides operands from interstage pipeline registers directly to the inputs of the function units. The power optimization technique exploits the forwarding paths to avoid the power cost of writing/reading short-lived variables to/from the register file (RF). Such optimization is justified by the fact that, in application-specific embedded systems, a significant number of variables are short-lived, that is, their liveness (from first definition to last use) spans only few instructions. Values of short-lived variables can thus be accessed directly through the forwarding registers, avoiding writeback to the RF by the producer instruction and successive read from the RF by the consumer instruction. The decision concerning the enabling of the RF writeback phase is taken at compile time by the compiler static scheduling algorithm. This approach implies a minimal overhead on the complexity of the processor control logic and, thus, no critical path increase. The application of the proposed solution to a VLIW embedded core has shown an average RF power saving of 7.8% with respect to the unoptimized approach on the given set of target benchmarks.

A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors

This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the dominant factors in the SoC energy budget (i.e., main memory access and high throughput global bus). Based on a differential technique, both the new algorithm and the HW compression unit have been developed to efficiently manage data compression and decompression into a high performance industrial processor architecture, under strict real time constraints (Lx-ST200: a 4-issue, 6-stage pipelined VLIW processor with on-chip D and I-cache). The original data-cache line is compressed before write-back to main memory and, then, decompressed whenever cache refill takes place. An extensive experimental strategy has been developed for the specific validation of the target Lx processor. In order to allow public comparison, we also report the results obtained on a MIPS pipelined RISC processor simulated with SimpleScalar. The two platforms have been benchmarked over Ptolemy and MediaBench programs. Energy savings provided by the application of the proposed technique range from 10% to 22% on the Lx-ST200 platform and from 11% to 14% on the MIPS platform.

Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors

Main goal of the paper is introducing a dynamic branch prediction scheme suitable for energy-aware VLIW (Very Long Instruction Word) processors. The proposed technique is based on a compiler hint mechanism to filter the accesses to the branch predictor blocks. Experimental results have been carried out on Lx/ST200, an industrial 4-issue VLIW architecture. We gathered two sets of results: First, by introducing the proposed low-power branch prediction technique in the Lx processor, which features fully static branch prediction, a significant improvement of the energy-delay metric has been observed. Second, we evaluated filtering efficacy of the proposed method and we found that it gets an access reduction to the branch prediction unit of 93% with respect to a processor directly derived from Lx, featuring cycle-by-cycle prediction, corresponding to an average 9% energy reduction of the whole processor power budget.

Automatic characterization and modeling of power consumption in static RAMs

An automatic modeling technique is presented in this paper that allows one to build an accurate model of power consumption in embedded memory blocks. A software neural-network is used to create a regression tree by automatically splitting those variables that have a discontinuous effect on the power consumption. An application of the methodology to the modeling of a 0.35 /spl mu/m CMOS embedded SRAM is presented.

Internet of Energy – Connecting Energy Anywhere Anytime

The forthcoming Smart Grid is expected to implement a new concept of transmission network which is able to efficiently route the energy produced from both concentrated and distributed plants up to the final user with high security and quality of supply standards. Therefore the Smart Grid is expected to be the implementation of a kind of “internet” in which the energy packets are managed similarly to data packets, across routers and gateways which autonomously can decide the best pathway for the packet to reach its destination with the best integrity levels. In this respect the “Internet of Energy” concept is defined as a network infrastructure based on standard and interoperable communication transceivers, gateways and protocols that allow a real time balance between the local and the global generation and storage capability with the energy demand, also allowing high level of consumer awareness and involvement. This paper presents some basic concept of the Internet of Energy and, in particular, its impact on Electric Mobility.

A Framework for Modeling and Estimating the Energy Dissipation of VLIW-Based Embedded Systems

This paper describes a technique for modeling and estimating the power consumptionat the system-level for embedded VLIW (Very Long Instruction Word) architectures.The method is based on a hierarchy of dynamic power estimationengines: from the instruction-level down to the gate/transistor-level. Powermacro-models have been developed for the main components of the system: theVLIW core, the register file, the instruction and data caches. The main goalis to define a system-level simulation framework for the dynamic profilingof the power behavior during the software execution, providing also a break-downof the power contributions due to the single components of the system. Theproposed approach has been applied to the Lx family of scalable embedded VLIWprocessors, jointly designed by STMicroelectronics and HPLabs. Experimentalresults, carried out over a set of benchmarks for embedded multimedia applications,have demonstrated an average accuracy of 5% of the instruction-level estimationengine with respect to the RTL engine, with an average speed-up of four ordersof magnitude.

Advanced Model for Fast Assessment of Piezoelectric Micro Energy Harvesters

The purpose of this work is to present recent advances in modelling and design of piezoelectric energy harvesters, in the framework of Micro-Electro-Mechanical Systems (MEMS). More specifically, the case of inertial energy harvesting is considered, in the sense that the kinetic energy due to environmental vibration is transformed into electrical energy by means of piezoelectric transduction. The execution of numerical analyses is greatly important in order to predict the actual behaviour of MEMS devices and to carry out the optimization process. In the common practice, the results are obtained by means of burdensome 3D Finite Element Analyses (FEA). The case of beams could be treated by applying 1D models, which can enormously reduce the computational burden with obvious benefits in the case of repeated analyses. Unfortunately, the presence of piezoelectric coupling may entail some serious issues in view of its intrinsically three-dimensional behaviour. In this paper, a refined, yet simple, model is proposed with the objective of retaining the Euler-Bernoulli beam model, with the inclusion of effects connected to the actual three-dimensional shape of the device. The proposed model is adopted to evaluate the performances of realistic harvesters, both in the case of harmonic excitation and for impulsive loads.