Rochit Rajsuman

Testing a system-on-a-chip with embedded microprocessor

In this paper, we describe the test methodology for embedded cores based system-on-a-chip (SoC) which contains a microprocessor core. First the microprocessor core is tested for correctness of all the instructions and then the computation power of the microprocessor core is used to test the on-chip memories and other cores, A small Iddq test set is also used to detect physical defects. The design features to facilitate Iddq testing are described.

Rambist builder: a methodology for automatic built-in self-test design of embedded rams

In this paper, we report a built-in self-test methodology for embedded RAMs. A CAD tool has been developed to synthesize the BIST circuitry for the compiled RAMs. The blocks such as address generator, pattern generator, multiplexers, state machine, control logic and comparator are automatically synthesized with this tool. The BIST logic is personalized to the RAM configuration and its physical bit map. This provides coverage of all stuck-at, state transition and coupling faults. In multi-port RAMs port-coupling faults are also detected. RAM addresses are generated by the address generator based upon the March algorithm. A set of multiplexers selects the path to the address, data and control lines, either from the RAM (during normal operation), or from the pattern generator (during test mode). The state machine and control logic provide signals for read, write, port selection and start/end. A comparator evaluates the data written during the write cycle against the RAMs output data to generate a pass/fail flag.

A new paradigm in test for the next millennium

In this paper we describe the architecture and implementation of a true simulation-direct-to-test event based tester. This tester uses event based design simulation data in the VCD form. This data is used as-is without requiring tester cyclization. It is a true per pin tester that can significantly shorten test complexity and time-to-market.

Open architecture test system: system architecture and design

The open architecture test system provides a method and framework under which software and instruments of different vendors can be developed and integrated into an ATE. In This work, we describe the overall architecture and design of the system. First we describe the architecture and the control mechanism for the overall system and for individual test-sites. Data and command communication mechanism among these control elements is explained. After this general structure, we describe how this architecture allows deployment of third party instruments and modules, what are the interfaces, how system is configured and how correct operation of the system is ensured after plugging-in a third party module.

Challenge of the 90's: testing CoreWare/sup (TM/) based ASICs

Testing of CoreWare based ASICs is emerging as the most challenging problem of the 1990s. The testing challenge is two fold: first, how to test the embedded cores; and second, how to integrate the test-set of a core with other blocks into ASIC level test-set. Each of these problems is further compounded by the Intellectual Property (IP) protection issue.