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Dive into the research topics where Rocio Contreras-Guerrero is active.

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Featured researches published by Rocio Contreras-Guerrero.


Applied Physics Letters | 2013

Properties of epitaxial BaTiO3 deposited on GaAs

Rocio Contreras-Guerrero; Joshua P. Veazey; Jeremy Levy; R. Droopad

Single crystal BaTiO3 (BTO) has been grown epitaxially on GaAs using molecular beam epitaxy with a 2 unit cell SrTiO3 nucleation layer. The oxide film is lattice-matched to GaAs through an in-plane rotation of 45° relative to the (100) surface leading to c-axis orientation of the BaTiO3. X-ray diffraction confirmed the crystallinity and orientation of the oxide film with a full width half maximum of 0.58° for a 7.5 nm thick layer. Piezoresponse force microscopy was used to characterize the ferroelectric domains in the BaTiO3 layer, and a coercive voltage of 1–2 V and piezoresponse amplitude ∼5 pm/V was measured.


Applied Physics Letters | 2013

InAs hole inversion and bandgap interface state density of 2 x 10(11) cm(-2) eV(-1) at HfO2/InAs interfaces

Chien-Hsun Wang; S. W. Wang; G. Doornbos; Gvidas Astromskas; K. Bhuwalka; Rocio Contreras-Guerrero; M. Edirisooriya; Juan Salvador Rojas-Ramirez; G. Vellianitis; R. Oxland; M. Holland; Chih-Hua Hsieh; Peter Ramvall; Erik Lind; Wei-Chou Hsu; Lars-Erik Wernersson; R. Droopad; M. Passlack; Carlos H. Diaz

High-k/InAs interfaces have been manufactured using InAs surface oxygen termination and low temperature atomic layer deposition of HfO2. Capacitance–voltage (C–V) curves revert to essentially classical shape revealing mobile carrier response in accumulation and depletion, hole inversion is observed, and predicted minority carrier response frequency in the hundred kHz range is experimentally confirmed; reference samples using conventional techniques show a trap dominated capacitance response. C–V curves have been fitted using advanced models including nonparabolicity and Fermi-Dirac distribution. For an equivalent oxide thickness of 1.3 nm, an interface state density Dit = 2.2 × 1011 cm−2 eV−1 has been obtained throughout the InAs bandgap.


IEEE Transactions on Electron Devices | 2015

Field-Effect Mobility of InAs Surface Channel nMOSFET With Low

S. W. Wang; Timothy Vasen; G. Doornbos; R. Oxland; Shang-Wen Chang; Xu Li; Rocio Contreras-Guerrero; M. Holland; Chien-Hsun Wang; M. Edirisooriya; Juan Salvador Rojas-Ramirez; Peter Ramvall; S. Thoms; D.S. Macintyre; G. Vellianitis; Gordon Hsieh; Yang-Sih Chang; Kaimin M. Yin; Yee-Chia Yeo; Carlos H. Diaz; R. Droopad; I.G. Thayne; M. Passlack

Frequency (100 Hz ≤ f ≤ 1 MHz) and temperature (-50 ≤ T 20 °C) characteristics of low interface state density D<sub>it</sub> high-κ gate-stacks on n-InAs have been investigated. Capacitance-voltage (C-V) curves exhibit typical accumulation/depletion/inversion behavior with midgap D<sub>it</sub> of 2 × 10<sup>11</sup> and 4 × 10<sup>11</sup> cm<sup>-2</sup> eV<sup>-1</sup> at -50 °C and 20 °C, respectively. Asymmetry of low-frequency C-V curves and C-T dependence for negative voltage showing a sharp transition of ≅-20 dB/decade between low- and high-frequency behavior indicate surface inversion. An inversion carrier activation energy and an InAs hole lifetime of 0.32 eV and 2 ns have been extracted, respectively. Surface channel nMOSFETs with gate length L<sub>g</sub> = 1 μm, channel thickness = 10 nm, and equivalent oxide thickness (EOT) 1 ≤ EOT ≤ 1.6 nm have been fabricated. For EOT = 1 nm, a subthreshold swing S = 65 mV/decade, transconductance g<sub>m</sub> = 1.6 mS/μm, and ON-current I<sub>ON</sub> = 426 μA/μm at an OFF-current I<sub>OFF</sub> = 100 nA/μm (supply voltage V<sub>dd</sub> = 0.5 V) have been measured. Peak electron field-effect mobilities of 6000-7000 cm<sup>2</sup>/Vs at sheet electron densities of 2-3 × 10<sup>12</sup> cm<sup>-2</sup> were obtained for EOT as small as 1 nm.


IEEE Electron Device Letters | 2016

D_{\rm it}

R. Oxland; Xu Li; S. W. Chang; Shyh-Wei Wang; T. Vasen; P. Ramvall; Rocio Contreras-Guerrero; Juan Salvador Rojas-Ramirez; M. Holland; G. Doornbos; Y. S. Chang; D.S. Macintyre; S. Thoms; R. Droopad; Yee-Chia Yeo; Carlos H. Diaz; I.G. Thayne; Matthias Passlack

We report the first demonstration of InAs FinFETs with fin width W<sub>fin</sub> in the range 25-35 nm, formed by inductively coupled plasma etching. The channel comprises defect-free, lattice-matched InAs with fin height H<sub>fin</sub> = 20 nm controlled by the use of an etch stop layer incorporated into the device heterostructure. For a gate length L<sub>g</sub> = 1 μm, peak transconductance gm,peak = 1430 μS/μm is measured at V<sub>d</sub> = 0.5 V demonstrating that electron transport in InAs fins can match planar devices.


Applied Physics Letters | 2014

Scaled Gate-Stack

Matthias Passlack; S. W. Wang; G. Doornbos; Chien-Hsun Wang; Rocio Contreras-Guerrero; M. Edirisooriya; Juan Salvador Rojas-Ramirez; Chih-Hua Hsieh; R. Droopad; Carlos H. Diaz

One of the major challenges of high mobility complementary metal-oxide-semiconductor (CMOS) circuits is to meet off-current requirements of <100 pA/μm for low stand-by power (LSTP) operation due to the small bandgap (≤0.5 eV) of the channel material (bandgap limit). In this work, we present experimental proof that the bandgap limit can be overcome at nanometer dimensions leveraging the phenomenon of steady state deep depletion (SSDD). The occurrence of SSDD is investigated using high-k capacitors with 5 and 10 nm InAs channel on a n- or p-type doped lattice matched wide bandgap AlAsSb layer. Absence of charge carriers at the off-state band edge is observed for 5 nm InAs channel layers demonstrating occurrence of SSDD and lifting of the off-state bandgap limit providing a path to meet LSTP requirements for future high mobility CMOS.


IEEE Transactions on Electron Devices | 2015

InAs FinFETs With

Paul Thomas; Matthew J. Filmer; Abhinav Gaur; D. Pawlik; Brian Romanczyk; Enri Marini; Sean L. Rommel; Kausik Majumdar; Wei-Yip Loh; Man Hoi Wong; C. Hobbs; Kunal Bhatnagar; Rocio Contreras-Guerrero; R. Droopad

In<sub>0.53</sub>Ga<sub>0.47</sub>As Esaki tunnel diodes grown by molecular beam epitaxy on an Si substrate via a graded buffer and control In<sub>0.53</sub>Ga<sub>0.47</sub>As Esaki tunnel diodes grown on an InP substrate are compared in this paper. Statistics are used as a tool to show peak-to-valley ratio for the III-V on Si sample and the control that perform similarly below 8.6 × 10<sup>-10</sup> cm<sup>-2</sup>. The existence of a critical device area suggests the potential to utilize III-V on Si for other deeply scaled tunnel devices.


Applied Physics Letters | 2014

\textrm {H}_{\mathrm {fin}}=20

Uthayasankaran Peralagu; Ian M. Povey; Patrick Carolan; Jun Lin; Rocio Contreras-Guerrero; R. Droopad; Paul K. Hurley; I.G. Thayne

In this work, the impact of ammonium sulfide ((NH4)2S) surface treatment on the electrical passivation of the Al2O3/p-GaSb interface is studied for varying sulfide concentrations. Prior to atomic layer deposition of Al2O3, GaSb surfaces were treated in 1%, 5%, 10%, and 22% (NH4)2S solutions for 10 min at 295 K. The smallest stretch-out and flatband voltage shifts coupled with the largest capacitance swing, as indicated by capacitance-voltage (CV) measurements, were obtained for the 1% treatment. The resulting interface defect trap density (Dit) distribution showed a minimum value of 4 × 1012 cm−2eV−1 at Ev + 0.27 eV. Transmission electron microscopy and atomic force microscopy examination revealed the formation of interfacial layers and increased roughness at the Al2O3/p-GaSb interface of samples treated with 10% and 22% (NH4)2S. In combination, these effects degrade the interface quality as reflected in the CV characteristics.


Applied Physics Letters | 2015

nm Fabricated Using a Top–Down Etch Process

Qiao Qiao; Yu-Yang Zhang; Rocio Contreras-Guerrero; R. Droopad; Sokrates T. Pantelides; Stephen J. Pennycook; Serdar Ogut; Robert F. Klie

The integration of functional oxide thin-films on compound semiconductors can lead to a class of reconfigurable spin-based optoelectronic devices if defect-free, fully reversible active layers are stabilized. However, previous first-principles calculations predicted that SrTiO3 thin films grown on Si exhibit pinned ferroelectric behavior that is not switchable, due to the presence of interfacial vacancies. Meanwhile, piezoresponse force microscopy measurements have demonstrated ferroelectricity in BaTiO3 grown on semiconductor substrates. The presence of interfacial oxygen vacancies in such complex-oxide/semiconductor systems remains unexplored, and their effect on ferroelectricity is controversial. Here, we use a combination of aberration-corrected scanning transmission electron microscopy and first-principles density functional theory modeling to examine the role of interfacial oxygen vacancies on the ferroelectric polarization of a BaTiO3 thin film grown on GaAs. We demonstrate that interfacial oxygen ...


international electron devices meeting | 2013

Lifting the off-state bandgap limit in InAs channel metal-oxide-semiconductor heterostructures of nanometer dimensions

Shou-Zen Chang; Xu Li; R. Oxland; S. W. Wang; C. H. Wang; Rocio Contreras-Guerrero; K. Bhuwalka; G. Doornbos; Tim Vasen; M. Holland; G. Vellianitis; M.J.H. van Dal; B. Duriez; M. Edirisooriya; Juan Salvador Rojas-Ramirez; P. Ramvall; S. Thoms; U. Peralagu; C.H. Hsieh; Y. S. Chang; K. M. Yin; Erik Lind; Lars-Erik Wernersson; R. Droopad; I.G. Thayne; M. Passlack; Carlos H. Diaz

Record setting III-V MOSFETs are reported. For the first time performance better than state-of-the-art HEMTs is demonstrated. For a MOSFET with 10 nm unstrained InAs surface channel and L<sub>g</sub> = 130 nm operating at 0.5 V, on-current as high as I<sub>on</sub> = 601 μA/μm (at fixed I<sub>off</sub> = 100 nA/μm) is achieved. This record performance is enabled by g<sub>m, ext</sub> = 2.72 mS/μm and S = 85 mV/dec, DIBL = 40 mV/V, resulting from breakthroughs in epitaxy and III-V/dielectric interface engineering. Measured mobility is 7100 cm<sup>2</sup>/V.s at n<sub>s</sub> = 6.7×10<sup>12</sup> cm<sup>-2</sup>. Device simulations further elucidate the performance potential of III-V N-MOSFETs.


IEEE Electron Device Letters | 2014

Performance Evaluation of In 0.53 Ga 0.47 As Esaki Tunnel Diodes on Silicon and InP Substrates

K. Bhuwalka; S. W. Wang; Odille C. Noriega; M. Holland; Rocio Contreras-Guerrero; Madavie Edirisooriya; G. Doornbos; Chien-Hsun Wang; Thomas H. Myers; R. Droopad; M. Passlack; Carlos H. Diaz

Electrical interface quality of various high- k dielectrics on GaSb, including Al<sub>2</sub>O<sub>3</sub>, HfO<sub>2</sub>, LaAlO<sub>3</sub>, GdScO<sub>3</sub>, and HfO<sub>2</sub>/Ga<sub>2</sub>O<sub>3</sub> bilayer has been studied and compared with reference low (AlGaSb) and high D<sub>it</sub> (native oxide) interfaces using photoluminescence intensity measurements for the first time. Al<sub>2</sub>O<sub>3</sub> and HfO<sub>2</sub>/Ga<sub>2</sub>O<sub>3</sub> bilayer dielectrics are identified with the lowest interface recombination velocity (S=7×10<sup>4</sup> cm/s) and consequently D<sub>it</sub> integrated across essentially the entire bandgap. However, S for even the best identified high- k dielectrics is elevated by 140× over the low D<sub>it</sub> AlGaSb reference indicating the need of further improvements for envisioned use in Sb based MOSFETs.

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R. Droopad

Texas State University

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G. Doornbos

Katholieke Universiteit Leuven

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S. W. Wang

Katholieke Universiteit Leuven

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Robert F. Klie

University of Illinois at Chicago

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M. Holland

Katholieke Universiteit Leuven

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M. Passlack

Katholieke Universiteit Leuven

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Qiao Qiao

University of Illinois at Chicago

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