Roderick Yap

Design, development and implementation of a fuzzy logic controller for DC-DC Buck and Boost converter in an FPGA

A fuzzy logic controller for DC-DC Buck and Boost converters is designed and presented in this paper. The mathematical model of buck and boost converter and fuzzy logic controller are first derived then converted to a hardware model using VHSIC Hardware Description Language. The hardware model was subsequently synthesized and implemented in a Field programmable Gate Array (FPGA) chip. In order to confirm that the mathematical model gives stable output frequency, simulation on MATLAB is made. To verify the effectiveness of the simulation model, an experimental set up is developed. An FPGA-based fuzzy logic controller was implemented and interfaced to a DC-DC converter module. The system was tested using white LEDs as loads. Simulation and experimental results show that the DC-DC converter is able to maintain the output based on the value set inside the controller module.

FPGA implementation of an indoor broadband power line channel emulator

Power line communication is an emerging technology in the field of communications that aims to use the power line as a medium to send and receive data. Several studies have been conducted to characterize the power lines [1], [2], [3], [4],. These studies guide PLC modem designers to create a more robust design. However, it is not practicable to test modems in a live power line network. This research aims to create an emulator capable of replicating the behavior of a typical indoor power line channel and use it as a test bed for PLC modem The emulator is implemented on Virtex 6 FPGA and FMC 151 for the analog front end. The power line channel model uses Zimmermans channel transfer function [5] as reference. Analysis are done by comparing theoretical results with the hardware results which are done in MATLAB and Xilinx respectively. Several features such as addition of noise are also within the emulator and can be selected by the user to improve the realism of the emulator. Lastly, channel parameters such as SNR (signal to noise ratio) and RMS (root mean square) delay spread are obtained to ensure the quality of the channel produced.

Design and characterization of fully integrated low frequency, low voltage 0.25μm CMOS clock generator circuit

When designing an integrated circuit, simulation should normally pass through 5 corner libraries. The ideal case is to have the simulation results showing the same performance for all the corner libraries. However, owing to the difference in specifications among libraries, there can be significant variations of one result over another per library. In this paper, a fully integrated CMOS RC Clock circuit topology design is presented. The circuit was designed to have minimal sensitivity to process corner library variations. The design can operate at a low voltage of 1.5V using the 0.25um library. Simulation shows the clock output frequency remains stable at 50 kHz for all process corner libraries with a maximum deviation of only 6%. An added feature of the circuit is the variation of the clocks duty cycle. The entire design is fitted in an area of 1.11um2.

Design and Development of Audit Central Data Bank at Ibiden Philippines, Inc. (IPI)

In most of the companies in the Philippines, audit findings and results are monitored manually. This method offers inaccessible and unreliable data that invokes downtime in audit issuance, audit response, audit verification and implementation, and audit closure as well. It showcased a process system of less priority and consideration on Productivity, Quality, Cost, Delivery and Morale. The proponent thought of a way to develop a central repository or data bank of audit findings to easily retrieve the audits conducted by IQA, PQA, IEA, TPM and other auditing bodies and to provide robust monitoring of Audit Issuance, Audit Response, Audit Verification (Verification of Implementation) and Audit Closure (Verification of Effectiveness). Audit Central Data Bank in Ibiden Philippines, Inc. is a PC-based centralized macro program. It is software that consolidates all audit results of each auditing body (IQA, PQA, IEA, TPM, YIP and External Supplier). It performs common tasks and functions understood and applied by entire IPI community.