Roger May

Embedded processor with watchdog timer for programmable logic

Bus architecture for system on a chip

I/O circuitry shared between processor and programmable logic portions of an integrated circuit

Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream

Embedded processor with dual-port SRAM for programmable logic

Updating configuration for programmable logic device

Re-configurable memory map for a system on a chip

Configuring memory and registers from a serial device

Address decoder for programmable logic device

Video processing architecture