Ronald I. Greenberg

Randomized routing on fat-tress

Fat-trees are a class of routing networks for hardwareefficient parallel computation. This paper presents a randomized algorithm for routing messages on a fat-tree. The quality of the algorithm is measured in terms of the load factor of a set of messages to be routed, which is a lower bound on the time required to deliver the messages. We show that if a set of messages has load factor λ = Ω(lg n lg lg n) on a fat-tree with n processors, the number of delivery cycles (routing attempts) that the algorithm requires is O(λ) with probability 1-O(1/n). The best previous bound was O(λ lg n) for the off-line problem where switch settings can be determined in advance. In a VLSI-like model where hardware cost is equated with physical volume, we use the routing algorithm to demonstrate that fat-trees are universal routing networks in the sense that any routing network can be efficiently simulated by a fat-tree of comparable hardware cost.

The fat-pyramid and universal parallel computation independent of wire delay

This paper shows that a fat-pyramid of area /spl Theta/(A) requires only O(log A) slowdown to simulate any competing network of area A under very general conditions. The result holds regardless of the processor size (amount of attached memory) and number of processors in the competing networks as long as the limitation on total area is met. Furthermore, the result is valid regardless of the relationship between wire length and wire delay. We especially focus on elimination of the common simplifying assumption that unit time suffices to traverse a wire regardless of its length, since the assumption becomes more and more untenable as the size of parallel systems increases. This paper concentrates on simulation using transmission lines (wires along which bits can be pipelined) with the message routing schedule set up off line, but it also discusses the extension to on-line simulation. This paper also examines the capabilities of a fat-pyramid when matched against a substantially larger network and points out the surprising difficulty of doing such a comparison without the unit wire delay assumption. >

An improved analytical model for wormhole routed networks with application to butterfly fat-trees

A performance model for wormhole routed interconnection networks is presented and applied to the butterfly fat-tree network. Experimental results agree very closely over a wide range of load rate. Novel aspects of the model, leading to accurate and simple performance predictions, include: (1) use of multiple-server queues, and (2) a general method of correcting queuing results based on Poisson arrivals to apply to wormhole routing. These ideas can also be applied to other networks.

Foliage arthropod communities of crop and fallow fields

SummaryTwo crop fields (alfalfa and orchard grass) and two fallow fields (bluegrass and old field) were compared on the basis of plant and foliage arthropod complexity. Plant species richness and foliage height diversity increased substantially from crop to fallow: bluegrass to fallow: old field. The trend in arthropod complexity paralleled this trend in plant complexity but dit not appear to be as striking. Fallow fields typically possessed more species, fever individuals, higher evenness in relative abundance patterns and proportionally more predators. However, crop fields had quite diverse foliage arthropod faunas, and we suggest that high primary productivity of crop fields may somewhat offset lowered plant habitat complexity.

On the area of hypercube layouts

This paper precisely analyzes the wire density and required area in standard layout styles for the hypercube. It shows that the most natural, regular layout of a hypercube of N2 nodes in the plane, in an N × N grid arrangement, uses [2N/3] + 1 horizontal wiring tracks for each row of nodes. (In the process, we see that the number of tracks per row can be reduced by 1 with a less regular design, as can also be seen from an independent argument of Bezrukov et al.) This paper also gives a simple formula for the wire density at any cut position and a full characterization of all places where the wire density is maximized (which does not occur at the bisection).

The Impact of the Exploring Computer Science Instructional Model in Chicago Public Schools

As part of the Taste of Computing project, the Exploring Computer Science (ECS) instructional model has been expanded to many high schools in the Chicago Public Schools system. The authors report on initial outcomes showing that students value the ECS course experience, resulting in increased awareness of and interest in the field of computer science. The authors also compare these results by race and gender. The data provide a good basis for exploring the impact of meaningful computer science instruction on students from groups underrepresented in computing; of several hundred students surveyed, nearly half were female, and over half were Hispanic or African American.

Minimum separation for single-layer channel routing

Abstract We present a linear-time algorithm for determining the minimum height of a single-layer routing channel. The algorithm handles single-sided connections and multiterminal nets. It yields a simple routability test for single-layer switchboxes, correcting an error in the literature.

Minimizing channel density with movable terminals

Algorithms to minimize density for channels with terminals that are movable subject to certain constraints are given. The main cases considered are channels with linear order constraints, channels with linear order constraints and separation constraints, channels with movable modules containing fixed terminals, and channels with movable modules and terminals. In each case, previous results for running time and space are improved by a factor of L/lg n and L, respectively, where L is the channel length and n is the number of terminals.<<ETX>>

On the difficulty of Manhattan channel routing

Abstract We show that channel routing in the Manhattan model remains difficult even when all nets are single-sided. Given a set of n single-sided nets, we consider the problem of determining the minimum number of tracks required to obtain a dogleg-free routing. In addition to showing that the decision version of the problem isNP-complete, we show that there are problems requiring at least d+Ω( n ) tracks, where d is the density. This existential lower bound does not follow from any of the known lower bounds in the literature.

Single-layer channel routing and placement with single-sided nets

Abstract This paper considers the optimal offset, feasible offset, and optimal placement problems for a more general form of single-layer VLSI channel routing than has usually been considered in the past. Most prior works require that every net has exactly one terminal on each side of the channel. As long as only one side of the channel contains multiple terminals of the same net, we provide linear-time solutions to all three problems. Such results are implausible, if the placement of terminals is entirely unrestricted; in fact, the size of the output for the feasible offset problem may be ω ( n 2 ). The linear-time results also hold with a ragged boundary on the side of the channel with multiple connections to the same net.