Ronald Koster

A low-power, ultra-low capacitance BICMOS process applied to a 2 GHz low-noise amplifier

A BICMOS process is presented that includes an ultra-low capacitance NPN bipolar transistor (PRET) together with conventional 10 GHz single-poly NPN and MOS devices. Isolation is done using shallow (STI) and deep trenches. The mechanism of capacitance reduction by STI is discussed. The PRET concept, with a 0.2 /spl mu/m-wide emitter is shown to yield record low capacitances (emitter/base: 1.5 fF, collector/base: 1 fF) combined with high-frequency capability (the cut-off frequency is 14 GHz). This concept is demonstrated in a 2 GHz low-noise amplifier. Proper functioning is obtained at a 3 times lower power consumption than previously reported in literature.

Poly-ridge emitter transistor (FRET): simple low-power option to a bipolar process

A new bipolar transistor structure is presented combining high-frequency performance with low power consumption. Processing is simple; only conventional steps are used. A comparison between the PRET and a similarly manufactured single-poly structure is made, involving simulations on device and circuit level and measurements on actual devices. The same high-frequency performance is obtained, the PRET consuming half the power of the single-poly device.<<ETX>>