Ronaldo Husemann

A Tutorial on H.264/SVC Scalable Video Coding and its Tradeoff between Quality, Coding Efficiency and Performance

The evolution of digital video technology and the continuous improvements in communication infrastructure is propelling a great number of interactive multimedia applications, such as real-time video conference, web video streaming and mobile TV, among others. The new possibilities on interactive video usage have created an exigent market of consumers, which demands the best video quality wherever they are and whatever their network support is (Schwarz et al., 2006). On this purpose, the transmitted video must match the receiver’s characteristics such as the required bit rate, resolution and frame rate, thus aiming to provide the best quality subject to receiver’s and network’s limitations. Besides, the same link is often used to transmit to either restricted devices such as small cell phones, or to high-performance equipments, e.g. HDTVworkstations. In addition, the stream should adapt to wireless lossy networks (Ohm, 2005). Based on this reasoning, these heterogeneous and non-deterministic networks represent a great problem for traditional video encoders which do not allow for on-the-fly video streaming adaptation. To circumvent this drawback, the concept of scalability for video coding has been lately proposed as an emergent solution for supporting, in a given network, endpoints with distinct video processing capabilities. The principle of a scalable video encoder is to break the conventional single-stream video in a multi-stream flow, composed by distinct and complementary components, often referred to as layers (Huang et al., 2007). Figure 1 illustrates this concept by depicting a transmitter encoding the input video sequence into three complementary layers. Therefore, receivers can select and decode different number of layers – each corresponding to distinct video characteristics – in accordance with the processing constraints of both the network and the device itself. The layered structure of any scalable video content can be defined as the combination of a base layer and several additional enhancement layers. The base layer corresponds to the lowest supported video performance, whereas the enhancement layers allow for the refinement of A Tutorial on H.264/SVC Scalable Video Coding and its Tradeoff between Quality, Coding Efficiency and Performance 1

Hardware integrated quantization solution for improvement of computational H.264 encoder module

The computational module of several MPEG-based video encoders, which includes the known algorithms of Discrete Cosine Transform, Hadamard Transform and Quantization, is widely used to identify and compress spatial redundancy in intra (raw input) or inter (computed residue) data pixel matrices. For some modern multimedia applications, like high definition (HD H.264/AVC) or scalable (H.264/SVC) encoder solutions, the demand for fast module implementations becomes critical. Practical experiments indicate that, inside a H.264 computational module, the quantization module normally represents a real bottleneck for fast hardware implementations. Considering that we propose a complete integrated solution of H.264 computational module, which incorporates the direct and inverse algorithms of Discrete Cosine Transform, Hadamard and Quantization with minimal communication delays. Also in this paper it is presented a practical study, considering distinct levels of parallelism for the quantization to demonstrate its influence in order to optimize global encoder complexity and performance. All proposed alternatives were designed using hardware description language VHDL and implemented into commercial FPGA boards to obtain experimental results.

A new multimedia synchronous distance learning system: the IVA study case

This paper presents an innovative distance learning system named IVA (Interactive Video and Audio) which allows users to access video content, from any electronic device with enough processing capability and resources, aiming an ubiquitous application (anytime and anywhere) through synchronous or asynchronous communication. The paper raises and discusses real issues about multipoint multimedia transmission, taking into account adaptation to differnt devices and different networks. The paper also discusses the implemented solutions to overcome the faced problems. The papers main focus is on live video transmission to many heterogeneous receivers, as this is the application which demands most resources from devices and network.

Tool support for evaluating temporal characteristics of industrial protocols

In fieldbus automation systems, the correctness of the real time behavior depends not only on the intra-device processing and process scheduling, but also on the inter-device communication that exchanges process variables information. The article presents a tool to evaluate temporal characteristics of industrial communication protocols. It can monitor runtime timing requirements of proposed communication, according to variable conditions affecting the communication, and present graphically time characteristics of the resulting validation. Two case studies, one evaluating the real time characteristics of the Foundation Fieldbus protocol and another one evaluating timing characteristics of the CSMA medium access protocol used are presented in order to validate the features of the presented tool.

Highly Efficient Transforms Module Solution for a H.264/SVC Encoder

The computational-intensive demands of H.264 video encoder normally imply to the use of high performance hardware solutions like dedicated multimedia DSP or programmable logic devices. These demands can be even more critical when it is necessary to implement a H.264/SVC (Scalable Video Coding) solution, an emergent encoder standard that provides the generation of flexible and adaptive multi-layer streams. The complexity of a SVC encoder increases proportionally with number of configured layers, introducing new challenges to multimedia market. In this work we propose an efficient hardware module, responsible for the transform algorithms (Hadamard and DCT) of a SVC encoder, processing up eight samples per clock. The proposed module take into account specific memory demands in order to produce an optimized solution with respect to encoder performance and complexity, aiming to reach a realizable SVC encoder.

Proposal of an improved motion estimation module for SVC

In October 2007 ITU-T and MPEG organizations published the Scalable Video Coding (SVC) specification as an addendum to the H.264 standard. Basically SVC enables H.264 video encoders to support temporal, spatial and SNR scalability. This new functionalities lead to more flexibility on bandwidth management and robustness against packet losses. It is therefore more suitable for heterogeneous multimedia applications like IPTV and mobile networks. However implementations of SVC specification are still limited due the augmented computational complexity. One of the most critical SVC algorithms is the motion estimation module, which allows identification of extra intra and inter-layer redundancies. The great computation demand of this module is responsible for the large SVC encoder latency time, restraining its use in real-time applications. We propose in this paper a new motion estimation approach specially designed to reduce memory accesses and data comparisons in order to increase performance. Experimental results prove significant gains in speed (up to 6 times faster) with small effects on quality (less than 0.2 dB).

New integrated architecture for H.264 Transform and Quantization hardware implementation

Due the computational complexity of video processing algorithms the practical implementation of modern video encoders, like H.264/SVC, normally demands for some kind of hardware acceleration. In this paper we present a new integrated computational hardware module, able to perform the H.264 encoder algorithms of Discrete Cosine Transform, Hadamard Transform and Quantization. All these hardware modules were jointly designed aiming to speed up encoder performance by optimizing timing synchronism, data handling and memory accesses. Particularly our integrated solution globally allows the complete processing of up to eight samples by clock of distinct data types (luma, blue or red chroma) for both inter or intra operations. The proposed project has been implemented for logic programmable technology using hardware description language (VHDL). Practical results obtained after synthesing and downloading the proposal into commercial FPGA boards confirms it as an innovative high performance hardware solution, adequate for real-time encoder implementation.

BR-Tool: a real-time bus monitoring and validation system for fieldbus-based industrial automation applications

This paper presents BR-Tool, a multi-protocol bus monitoring and temporal validation software developed to provide temporal validation of fieldbus-based automation applications. BR-Tool monitors communication on industrial networks during real operation and compares acquired data with temporal requirements previously specified. Two industrial case studies are presented in this paper: the first one is a PROFIBUS-DP based manufacturing system, and the second one deals with a energy control system application based on CANOpen protocol.

A multi-protocol on-line monitoring system for distributed automation systems

Abstract This work describes an on-line monitoring system that allows the evaluation of tilning characteristics of automation systems implemented as a distributed network based on fieldbus technology. The monitoring system is composed by a programmable message logging module. which supports different standardized industrial protocols, and a validation toolset responsible for requirement analysis, timing requirements checking, and graphical visualization of the results.

Optimized SAD calculation algorithm for Cell® processor

Recent multimedia applications demand very high performance to support real-time video encoding. More specifically the mechanism of image block matching is one of the most critical encoder algorithms in terms of computational costs. It is responsible by searching for similar pixel macroblocks when comparing the current macroblock with others in reference images. The SAD (Sum of Absolute Differences) calculation is largelly used as comparation method in different block matching algorithms. This paper purposes a new strategy of SAD method implementation optimized to modern DSP microprocessor architectures like IBM Cell®. Practical results of our proposed method in a H.264/AVC encoder indicate a gain of more than eigth times for each computing unit when compared with original reference code performance.