Rongxiang Wu

Modeling of Mutual Coupling Between Planar Inductors in Wireless Power Applications

This paper presents a compact model of mutual inductance between two planar inductors, which is essential to design and optimize a wireless power transmission system. The tracks of the planar inductors are modeled as constant current carrying filaments, and the mutual inductance between individual filaments is determined by Neumanns integral. The proposed model is derived by solving Neumanns integral using a series expansion technique. This model can predict the mutual inductance at various axial and lateral displacements. Mutual coupling between planar inductors is computed by a 3-D electromagnetic (EM) solver, and the proposed model shows good agreement with these numerical results. Different types of planar inductors were fabricated on a printed circuit board (PCB) or silicon wafer. Using these inductors, wireless power links were constructed for applications like implantable biomedical devices and contactless battery charging systems. Mutual inductance was measured for each of the cases, and the comparison shows that the proposed model can predict mutual coupling suitably.

A Novel Silicon-Embedded Coreless Inductor for High-Frequency Power Management Applications

In this letter, a novel post-CMOS silicon-embedded coreless power inductor is proposed and demonstrated. The inductor is fabricated in the thick bottom layer of a silicon substrate and connected to the front side through vias opened in the thin top layer where control circuits can be fabricated for chip area saving. A 0.8- coreless inductor fabricated using this monolithic inductor technology shows a low dc resistance of 87 and an inductance of 13.1 nH with a quality factor of 3.9 at 100 MHz. A high inductor efficiency of 93% was estimated for 2.4-1.5-V 0.6-A power conversion at 100 MHz. This technology is very suitable for power-supply-on-chip applications.

Silicon-Embedded Receiving Coil for High-Efficiency Wireless Power Transfer to Implantable Biomedical ICs

In this letter, a silicon-embedded receiving coil is designed and fabricated for high-efficiency wireless power transfer to implantable biomedical ICs. The 4.5 mm × 4.5 mm embedded receiving coil achieved a large inductance of 4 μH and a high peak quality factor of 20 at 2.8 MHz. Measurement results of an inductive power link using the embedded receiving coil and a conventional printed-circuit-board transmitting coil (2 cm × 2 cm) demonstrated peak voltage gains of 0.84 and 0.24 and peak efficiency values of 30% and 4.3% for separation distances of 5 and 12 mm, respectively. This is the best reported wireless power transmission efficiency for separation distance similar to the implant chip size.

Design and Characterization of Wireless Power Links for Brain–Machine Interface Applications

In this paper, the design of an inductive power link (IPL) for wireless power transfer (WPT) in brain-machine interface (BMI) applications is thoroughly studied. The constraints and requirements of BMI applications are analyzed. By theoretical derivations, the relationships between the IPL performances and its electrical parameters are determined. The design guidelines for the IPL physical parameters are then obtained through experimental characterizations. Experimental results show that with proper IPL design, the efficiency can be improved from the previously reported values of 29.9% and 4.3% to 33.1% and 9.2% for BMI WPT distances of 5 and 12.5 mm, respectively.

High-Efficiency Silicon-Embedded Coreless Coupled Inductors for Power Supply on Chip Applications

In this paper, high-efficiency silicon-embedded coreless coupled inductors are demonstrated for power supply on chip applications. The embedded coupled inductors have two interleaved thick inductor coils embedded in the bottom layer of the Si substrate and four copper vias formed in the top substrate layer. The embedded coupled inductors can be stacked underneath the active circuitry for compact on-chip integration, while small resistances can be achieved with the thick embedded coils, which lead to high efficiency. As a demonstration, embedded coupled inductors with a small area of 0.5 mm2 were designed and fabricated according to the on-chip dc-dc converter with the highest reported efficiency. The fabricated embedded coupled inductors show a much higher efficiency of 93% compared to the 84% efficiency of the originally used on-substrate coupled inductors, allowing the total converter loss to be reduced by 38% and the converter efficiency to be improved from 78% to 85%.

SJ-FINFET: A New Low Voltage Lateral Superjunction MOSFET

This paper proposes a new SOI lateral superjunction (SJ) power transistor structure, SJ-FINFET, to address the requirement for low voltage lateral MOSFETs with low specific on-resistance (Ron,sp). The SJ-FINFET consists of a 3D trench gate and a SJ drift region (the fin) to reduce both the channel resistance and the drift region resistance. The SJ-FINFET with n/p-drift region pillar thickness (SOI layer thickness, Tepi) of 4 mum was simulated and found to have a Ron,sp of 0.18 mOmegaldrcm2. This is 21% lower than the well-known silicon limit at a breakdown voltage (BVdss) of 68 V.

High-Q Backside Silicon-Embedded Inductor for Power Applications in /spl mu/H and MHz Range

In this paper, a set of backside silicon-embedded inductors (BSEIs) is fabricated and characterized for potential applications in next-generation fully integrated power electronics. The fabrication technology of the BSEI is very similar to the through-silicon-via technology and has a high potential for post-CMOS integration. Without using magnetic material, an inductance as high as 13.8 μH is achieved with an effective inductance density of 0.6 μH/mm2. For the 4.5 mm × 4.5 mm BSEIs with a high substrate resistivity, an inductance between 2 and 4 μH, a dc resistance of 0.6-1.4 Ω , and a peak quality factor ranging from 18 to 23 occurring at 2-5 MHz are experimentally demonstrated. The effects of various physical design parameters are also experimentally studied, including coil outer dimension, metal width/spacing/pitch, coil shape, and silicon resistivity. These measurement results illustrate the design flexibility of the proposed BSEI technology to allow tradeoffs of key electrical properties for meeting different requirements of various integrated power electronics.

A novel silicon-embedded coreless transformer for isolated DC-DC converter application

In this paper, a novel silicon-embedded coreless transformer (SECT) is proposed and demonstrated for isolated dc-dc converter applications. By embedding two interleaved thick Cu coils in the bottom layer of the Si substrate, the designed 2 mm2 SECT can achieve a maximum transformer efficiency of 85% at 50 MHz. Compared to the on-silicon coreless power transformer reported earlier for 0.5 W isolated dc-dc conversion at 170 MHz with a transformer efficiency of over 70%, the much lower operating frequency of the SECT allows the power losses of the power MOSFETs and Schottky diodes to be reduced by around 50%, leading to a converter loss reduction of 38%. Since only 4 vias are opened at the top layer of the substrate, most of the top layer of the substrate can be used for power IC implementation to achieve efficient monolithic integration. Experimental results show that the SECT provides a maximum transformer efficiency of 73% at 50 MHz, which is lower than expected and due to the non-optimized isolation oxide used.

Novel Silicon-Embedded Coreless Transformer for On-Chip Isolated Signal Transfer

In this letter, a novel silicon-embedded coreless transformer is proposed and demonstrated. The transformer is fabricated in the thick bottom layer of a silicon substrate and connected to the frontside through vias opened in the thin top layer where all other components of the system can be fabricated. A 5-turn coreless transformer fabricated using this monolithic transformer technology achieves a small area of 2 mm2 and a good voltage gain of larger than -0.8 dB (load = 50 Ω, best reported so far) from 12 to 100 MHz. This technology shows great potential for on-chip isolated signal transfer.

Wireless power link design using silicon-embedded inductors for brain-machine interface

This paper discusses the safety requirements, equivalent circuit model, and design strategy of wireless power transmission to neural implants. The most daunting challenge is the design of the integrated receiving coil on the implantable device whose size must be within the safety and regulation limits while providing sufficient power transfer and efficiency. A novel silicon substrate-embedded 3.6-μH spiral inductor has been designed to fit inside a 4.5 mm × 4.5 mm implantable IC as the receiving coil. Full-wave EM simulations show that in a practical brain-machine interface setting, wireless power in the range of 1-10 mW can be delivered at 5% efficiency to an implant at 1 cm below the head surface using signals between 2 to 5 MHz. To achieve a high transfer efficiency, the optimal impedance for loading the receiving coil is derived using the equivalent circuit parameters of a realistic 3D model of the entire wireless power link. The large parasitic capacitance of the “in-chip” inductor is methodically absorbed in the matching network to maximize the efficiency and power transfer.