Ronnie O. Serfa Juan

Development of burst error effect reduction algorithm for CAN using interleaver method

A controller area network (CAN) controller is a critical component for immediate response in correcting certain flaws in any electronic control unit (ECU) especially in advanced driver assistance system (ADAS) application. This paper uses interleaving scheme to minimize the effect of Electro-Magnetic Interference (EMI) and aims to improve the system efficiency by improving the systems frame rate. This proposed method interleaved the original CAN data frame in order to minimize or totally eliminate the needed stuff bits that causes by the effect of EMI. The probability of error is reduced, thereby reducing also the probability of retransmission. The proposed scheme is synthesized on the Xilinx Virtex-5 FPGA.

Using DSP Algorithms for CRC in a CAN Controller

A controller area network (CAN) controller is an integral part of an electronic control unit, particularly in an advanced driver assistance system application, and its characteristics should always be advantageous in all aspects of functionality especially in real time application. The cost should be low, while maintaining the functionality and reliability of the technology. However, a CAN protocol implementing serial operation results in slow throughput, especially in a cyclical redundancy checking (CRC) unit. In this paper, digital signal processing (DSP) algorithms are implemented, namely pipelining, unfolding, and retiming the CAN controller in the CRC unit, particularly for the encoder and decoder sections. It must attain a feasible iteration bound, a critical path that is appropriate for a CAN system, and must obtain a superior design of a high-speed parallel circuit for the CRC unit in order to have a faster transmission rate. The source code for the encoder and decoder was formulated in the Verilog hardware description language.

Utilization of DSP algorithms for Cyclic Redundancy Checking (CRC) in Controller Area Network (CAN) controller

Controller Area Network (CAN) controller is an integral part of Electronic Control Unit (ECU) particularly in Advanced Driver Assistance System (ADAS) application, its characteristics should always be advantageous in all aspects of functionality. Primarily, the costing should be low but maintaining the reliability of this technology. However, CAN protocol is implementing serial operation resulting to a slow throughput. In this paper, we utilized the Digital Signal Processing (DSP) algorithms, namely pipelining, unfolding and retiming to CAN controller in Cyclic Redundancy Checking (CRC) unit particularly for Encoder and Decoder section in able to attain the feasible iteration bound, critical path that is appropriate for CAN system and to obtain superior design of a high speed parallel circuit for CRC. The source code for Encoder and Decoder has been formulated in Verilog Hardware Description Language (HDL).

Reconfiguration of an FPGA-Based Time-Triggered FlexRay Network Controller Using EEDC

Today, the demand of communication network, particularly in the automotive communication network, is experiencing a rapid evolution in terms of computing power and efficiency. The required standard should be faster and more reliable electronic vehicle systems. FlexRay is a time-triggered protocol that can cater these necessary specifications, especially for automotive applications such as advanced driver assistance systems. Also, any FPGA-based devices provide high performance to sustain the needs of higher functionality. This proposed controller uses a modified version of error detection code. Also, it is implemented in Xilinx Spartan 6 FPGA and can provide better functionality against existing controllers. Experimental results show a better performance in terms of data rate and reduction of resource utilization. Moreover, this implementation can represent an advancement in the FPGA-based system for vehicular applications.

FPGA implementation of hamming code for increasing the frame rate of CAN communication

Controller Area Network (CAN) protocol utilizes Cyclic Redundancy Check (CRC) code as a self-correcting method to detect and correct errors. The main objective of this algorithm is to use an alternative error correction scheme which is called as the Hamming code, replacing the conventional CRC code. Moreover, to possibly increase the CANs frame rate of the system. The bits positions of the redundant bits ‘r’ and the bit streams of the frames from the start-of-frame (SOF) to the control bit frames are determine. These bits will be fed into the redundant bit controller to compute for the necessary r. The redundant bits positions are in power of 2, and will be calculated using modulo-2 operation. This proposed method is synthesized using Xilinx Virtex-5 FPGA. The simulation results shows a significant increase of CANs frame rate and, it minimizes the bits stuffing payload and can be a better option for detecting and correcting error in CAN System.