Ronny Haupt

Improving OCD time to solution using Signal Response Metrology

In recent technology nodes, advanced process and novel integration scheme have challenged the precision limits of conventional metrology; with critical dimensions (CD) of device reduce to sub-nanometer region. Optical metrology has proved its capability to precisely detect intricate details on the complex structures, however, conventional RCWA-based (rigorous coupled wave analysis) scatterometry has the limitations of long time-to-results and lack of flexibility to adapt to wide process variations. Signal Response Metrology (SRM) is a new metrology technique targeted to alleviate the consumption of engineering and computation resources by eliminating geometric/dispersion modeling and spectral simulation from the workflow. This is achieved by directly correlating the spectra acquired from a set of wafers with known process variations encoded. In SPIE 2015, we presented the results of SRM application in lithography metrology and control [1], accomplished the mission of setting up a new measurement recipe of focus/dose monitoring in hours. This work will demonstrate our recent field exploration of SRM implementation in 20nm technology and beyond, including focus metrology for scanner control; post etch geometric profile measurement, and actual device profile metrology.

Influence of the process-induced asymmetry on the accuracy of overlay measurements

In the current paper we are addressing three questions relevant for accuracy: 1. Which target design has the best performance and depicts the behavior of the actual device? 2. Which metrology signal characteristics could help to distinguish between the target asymmetry related overlay shift and the real process related shift? 3. How does uncompensated asymmetry of the reference layer target, generated during after-litho processes, affect the propagation of overlay error through different layers? We are presenting the correlation between simulation data based on the optical properties of the measured stack and KLA-Tencor’s Archer overlay measurements on a 28nm product through several critical layers for those accuracy aspects.

Signal response metrology (SRM): a new approach for lithography metrology

CD uniformity requirements at 20nm and more advanced nodes have challenged the precision limits of CD-SEM metrology, conventionally used for scanner qualification and in-line focus/dose monitoring on product wafers. Optical CD metrology has consequently gained adoption for these applications because of its superior precision, but has been limited adopted, due to challenges with long time-to-results and robustness to process variation. Both of these challenges are due to the limitations imposed by geometric modeling of the photoresist (PR) profile as required by conventional RCWA-based scatterometry. Signal Response Metrology (SRM) is a new technique that obviates the need for geometric modeling by directly correlating focus, dose, and CD to the spectral response of a scatterometry tool. Consequently, it suggests superior accuracy and robustness to process variation for focus/dose monitoring, as well as reducing the time to set up a new measurement recipe from days to hours. This work describes the fundamental concepts of SRM and the results of its application to lithography metrology and control. These results include time to results and measurement performance data on Focus, Dose and CD measurements performed on real devices and on design rule metrology targets.

Etch process monitoring possibilities and root cause analysis

Tilt of the shallow trench isolation on the wafer edge with the radial signature is a known issue for all technology nodes. Presence of this tilt was proven by cross-sectional TEM measurements. For advanced nodes, starting from 28 nm, this tilt becomes one of the crucial yield-killer strongly influencing the performance of the edge dies. If this tilt is not corrected for, overlay values of all FEOL layers will include an error on the wafer edge which leads to low performance of the devices and possibly yield loss. The etch process is thought to be responsible for the tilt, however even for the simplest stack the mechanism and reason of the tilt is not clear. The ability to monitor this tilt in production opens a way for understanding this mechanism and even eliminate the root cause. In this paper we will present the opportunity to measure with Spectroscopic critical dimension (SCD) and Overlay-Accuracy flags the asymmetry of tilted etch structures as well as identify the possible root cause of the tilt by monitoring the nanotopography before and after the etch process.

Highly-stable four-point-probe metrology in implant and epitaxy processes

The resistivity (doping level) in epitaxial and implant layers has high impact on electrical device parameters of power semiconductors. However, precise control of electrical layer resistivity with the four-point-probe (4PP) technique is still challenging due to the contact between semiconductor layers with metal probes. In this work, the repeatability of 4PP sheet resistance (Rs) measurement on epitaxial and implant layers was studied. The results prove the excellent repeatability and reliability of sheet resistance metrology on the power semiconductor processing layers.

Overlay and stitching metrology for massively parallel electron-beam lithography (Conference Presentation)

One of the metrology challenges for massively parallel electron beams is to verify that all the beams that are used perform within specification. The Mapper FLX-1200 platform exposes fields horizontally segmented in 2.2 μm-wide stripes. This yields two parameters of interest: overlay is the registration error with respect to a previous layer, and stitching is the registration error between the stripes. This paper presents five novel overlay targets and one novel stitching target tailored for Mapper’s needs and measured on KLA-Tencor Archer 600 image based overlay (IBO) platform. The targets have been screened by exposure of a variable shaped electron beam lithography machine (Vistec VSB 3054 DW) on two different stacks: resist-to-resist and resist-to-etched silicon, both as a trilayer stack. These marks attain a total measurement uncertainty (TMU) down to 0.3 nm and move-and-measure (MAM) time down to 0.3 seconds for both stacks. The stitching targets have an effective TMU of 0.4 nm and a MAM time of 0.75 seconds. In a follow up experiment, the two best performing overlay targets have been incorporated in an exposure by a Mapper FLX-1200. With the new stack a TMU of 0.3 nm and MAM time of 0.35 s have been attained. For 107 out of 140 selected stripes the slope was constant within 2.5%, the offset smaller than 0.5 nm and correlation coefficient R2 > 0.98.

Matching between simulations and measurements as a key driver for reliable overlay target design

Numerical simulation of overlay metrology targets has become a de-facto standard in advanced technology nodes. While appropriate simulation software is widely available in the industry alongside with metrics that allow selection of the best performing targets, the model validation tools are less developed. We present an approach of numerical model validation based on the comparison between target simulation results and on-product overlay measurements. A “simulation-tomeasurement” software is used in this work to compare the performance metrics and accuracy flags of scatterometrybased overlay targets designed using KLA-Tencor AcuRate™ simulator for the critical layers of 12nm FD-SOI FEOL stack and 22nm FD-SOI BEOL stack. We demonstrate how simulation-to-measurement matching enabled us to verify the model, identify discrepancies between the model and the product stack and build an improved model that correctly describes the target. The refined target stack was used for image-based overlay target simulations that allowed us to obtain better performing optical overlay targets as well.

Feasibility of monitoring a multiple e-beam tool using scatterometry and machine learning: stitching error detection

Multiple electron beam direct write lithography is an emerging technology promising to address new markets, such as truly unique chips for security applications. The tool under consideration, the Mapper FLX-1200, exposes long 2.2 μm-wide zones called stripes by groups of 49 beams. The critical dimensions inside and the registration errors between the stripes, called stitching, are controlled by internal tool metrology. Additionally, there is great need for on-wafer metrology of critical dimension and stitching to monitor Mapper tool performance and validate the internal metrology. Optical Critical Dimension (OCD) metrology is a workhorse technique for various semiconductor manufacturing tools, such as deposition, etching, chemical-mechanical polishing and lithography machines. Previous works have shown the feasibility to measure the critical dimension of non-uniform targets by introducing an effective CD and shown that the non-uniformity can be quantified by a machine learning approach. This paper seeks to extend the previous work and presents a preliminary feasibility study to monitor stitching errors by measuring on a scatterometry tool with multiple optical channels. A wafer with OCD targets that mimic the various lithographic errors typical to the Mapper technology was created by variable shaped beam (VSB) e-beam lithography. The lithography process has been carefully tuned to minimize optically active systematic errors such as critical dimension gradients. The OCD targets contain horizontal and vertical gratings with a pitch of 100 nm and a nominal CD of 50 nm, and contain various stitching error types such as displacement in X, Y and diagonal gratings. Sensitivity to all stitching types has been shown. The DX targets showed non-linearity with respect to error size and typically were a factor of 3 less sensitive than the promising performance of DY targets. A similar performance difference has seen in nominally identical diagonal gratings exposed with vertical and horizontal lines, suggesting that OCD metrology for DX cannot be fully characterized due to lithography errors in gratings with vertical lines.

Image based overlay measurement improvements of 28nm FD-SOI CMOS front-end critical steps

Technology shrinkage leads to tight specifications in advanced semiconductor industries. For several years’, metrology for lithography has been a key technology to address this challenge and to improve yield. More specifically overlay metrology is the object of special attention for tool suppliers and semiconductor manufacturers. This work focuses on Image Based Overlay (IBO) metrology for 28 nm FD-SOI CMOS front-end critical steps (gate and contact). With Overlay specifications below 10 nm, accuracy of the measurement is critical. In this study we show specific cases where target designs need to be optimized in order to minimize process effects (CMP, etch, deposition, etc.) that could lead to overlay measurement errors. Another important aspect of the metrology target is that its design must be device-like in order to better control and correct overlay errors leading to yield loss. Methodologies to optimize overlay metrology recipes are also presented. If the process effects cannot be removed entirely by target design optimization, recipe parameters have to be carefully chosen and controlled to minimize the influence of the target imperfection on measured overlay. With target asymmetry being one of the main contributors to those residual overlay measurement errors the Qmerit accuracy flag can be used to quantify the measurement error and recipe parameters can be set accordingly in order to minimize the target asymmetry impact. Reference technique measurements (CD-SEM) were used to check accuracy of the optimized overlay measurements.

Addressing thin film thickness metrology challenges of 14nm BEOL layers

In this paper we discuss the impact of these two effects on the film thickness measurement and describe our approach to develop a film stack model and recipe which accounts for the underlying stack as well as Chemical Mechanical Planarization (CMP) variation. We also describe the verification and production implementation of this model using mass production data.