Roy L. Maddox

p-MOSFET parameters at cryogenic temperatures

p-channel MOSFET parameters measured at 300 K, 77 K, and 4.2 K are discussed; these include I-V characteristic curves, channel conductance, transconductance, threshold voltage, field effect mobility, and forward and reverse p+n junction characteristics. Some qualitative explanations of the dependence of the data on temperature and substrate doping concentration are given. Interesting LHe phenomena are highlighted and discussed in terms of accepted solid state models.

On the optimization of VLSI contacts

The contact-resistance characteristic of silicon devices has been a subject of research and development since the early days of silicon integrated-circuit technology. The contact-chain losses suffered by very large scale integration (VLSI), however, have made the minimization of contact resistance a critical parameter due to the large number of contacts per circuit and due to the increase of contact resistance with decreasing contact size. This paper will present a brief review of the theory of contact resistance, the literature, measurement techniques, and of the transmission-line model (TLM) for analyzing contact-resistance data. Contact-resistance data pertaining to shallow high-conductivity contacts for VLSI will be presented as a function of the junction parameters (implant dose, etc.) and of the contact area for BF2and arsenic implants with aluminum-silicon metallization. Contact-resistance data for a sputtered molybdenum silicide contact barrier for boron and arsenic implants versus contact area will also be presented and compared to the aluminum-silicon control samples with a discussion regarding the uniformity of contacts to silicon.

Electrical characterisation of ion-implanted silicon-on-sapphire

Electrical parameters of carrier transport in SOS films were investigated by measuring gate capacitance at frequencies ranging from 1kHz to 10MHz, conductance both in the linear region and in the saturation region and Hall effect as a function of gate bias voltage. The results show that the mobility decreases almost linearly with increasing distance from the Si/SiO2 interface. Similar characteristics were obtained for the carrier concentration profile. The magnitudes drop more than 200 percent from the Si/SiO2 interface to about 0.2μm deep in the Si film. This experimental result is very different from the data predicted by SUPREM. Spreading resistance profiles measured on the same n-type SOS film. after wafer processing show increasing resistivity with increasing distance from the Si surface. The doping profile calculated from spreading resistance data by using the mobility data obtained from the gated Hall effect measurements also indicates that the n-type carrier concentration decreases toward the Si/sapphire interface. The discrepancy between experimental data and the carrier concentration profile predicted by SUPREM can be explained by the existence of deep-level acceptor traps that are evident from Hall effect measurements made on a lightly boron-implanted SOS sample. The temperature dependence of the free carrier concentration shows an activation energy close to 0.31 eV. Mobility and carrier concentration measured by different techniques is discussed.

Oxidation through the zirconia substrates of heteroepitaxial silicon films Grown on yttria-stabilized cubic zirconia

We demonstrate the thermal oxidation of the Si side of the interface in epitaxial Si films grown on yttria-stabilized cubic zirconia, 〈Si〉/〈YSZ〉, to form a dual-layer structure of 〈Si〉 /amorphous SiO2/〈YSZ〉. The SiO2 films are formed in either dry oxygen (at 1100‡C) or in pyrogenic steam (at 925‡C) by the rapid diffusion of oxidizing species through the 425 Μm thick cubic zirconia substrate. For instance, a 0.17 Μm thick SiO2 layer is obtained after 100 min in pyrogenic steam at 925‡C. This relatively easy transport of oxidants is unique to YSZ and other insulators which are also superionic oxygen conductors, and cannot be achieved in other existing Si/insulator systems, such as Si-on-sapphire. The present process eliminates the most

The design and performance of near micron SOS MOSFETs

SOS MOSFETs with excellent high speed operation capability (>1GHz) have been designed using computer aided process design techniques and fabricated using state of the art processing technology. The process was optimised for 0.8 to 1.0μm channel length SOS devices. The subthreshold current slope of these devices pushes the theoretical limit at 60 millivolts per decade of current which is further evidenced by ring oscillator single stage delays as low as 85 picoseconds. The leakage current of these devices ranged from 1 to 20 picoamps at 1.0μm channel length as the channel width decreased from 10 to 2μm. Additional data is presented on the channel length and width dependence of the threshold voltage, source-drain breakdown voltage, effective channel mobility, and subthreshold current slope.

The new microelectronic processing technology: a review of the state-of-the-art

This paper discusses advances in the lithographic process. Emphasis will be on resist modelling, developing, and removal methods. Next, the various dry etching techniques are presented. The rest of the paper discusses processing advances outside the category of dry processing. This includes lift-off patterning, ion implantation techniques, laser annealing, RF annealing, and plasma deposition.

Channel doping profile of silicon‐on‐sapphire transistors

Dopant profiles of low‐dose channel implant in silicon‐on‐sapphire (SOS) field‐effect transistors are investigated by comparing results from various techniques, including theoretical calculation by the Stanford University integrated‐circuit process simulation program (suprem) and experimental measurements by secondary ion mass spectrometry (SIMS), capacitance‐voltage (C‐V), spreading resistance and metal‐oxide‐semiconductor Hall effect. It is shown that, for both phosphorus‐ and boron‐implanted SOS films having constant doping profile at a level close to 1×1016 cm−3, as predicted by suprem and measured by SIMS, the charge density measured by C‐V technique and free carrier concentration obtained from spreading resistance technique decrease with increasing distance from the Si surface. For SOS films implanted to a level greater than 1× 1017 cm−3 boron, the dopant profile obtained by SIMS analysis coincides with the charge density profile, measured by C‐V technique, and the free carrier concentration profile...

MOSFET performance enhancement by improved SOS material processes

The performance of NMOS/SOS devices designed for near micron geometries is shown to be enhanced markedly by pre-process SOS material improvements. A description of the double solid phase epitaxial regrowth technique, DSPE, is presented including the results of several materials evaluation, techniques: Rutherford backscattering and channeling spectrometry, X-ray twin content, sheet resistance, spreading resistance, ultraviolet reflectivity, and Hall data vs. temperature. Post-MOS process evaluation data of materials and device properties is also presented, which includes: gated Hall data, SIMS, sheet resistance, majority and minority carrier mobility, threshold voltage, subthreshold current slope, back channel leakage current, and electrical carrier density profiles. Significantly enhanced device performance is reported, such as ≥20% improvement in all mobilities, factor of 100 reduction in twin content, factor of 5 to 10 reduction in backchannel leakage, and 15 to 25% improvement in subthreshold current slope.

Fabrication process techniques for switched-capacitor filter circuits

Several different capacitor structures that are integratable to a production NMOS or N well CMOS process are described and discussed. The methods of fabrication for each major category of capacitor structure are presented along with some additional variations to each type of structure which will improve the quality of that capacitor structure. The pros and cons of each major type of structure are discussed with respect to device performance and ease of integration into the process. The properties of the capacitor dielectrics are discussed and data presented for oxide growth on polysilicon, breakdown voltage, leakage, and dissipation factor. The information presented is useful in providing a rational basis for switched capacitor filter design.