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Dive into the research topics where Roy W. Melton is active.

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Featured researches published by Roy W. Melton.


international symposium on neural networks | 2010

GPU-based simulation of spiking neural networks with real-time performance & high accuracy

Dmitri Yudanov; Muhammad Shaaban; Roy W. Melton; Leon Reznik

A novel GPU-based simulation of spiking neural networks is implemented as a hybrid system using Parker-Sochacki numerical integration method with adaptive order. Full single-precision floating-point accuracy for all model variables is achieved. The implementation is validated with exact matching of all neuron potential traces from GPU-based simulation versus those of a reference CPU-based simulation. A network of 4096 Izhikevich neurons simulated on an NVIDIA GTX260 device achieves real-time performance with a speedup of 9 compared to simulation executed on Opteron 285, 2.6-GHz device.


international conference on computer communications and networks | 2015

Privacy Sensitive Resource Access Monitoring for Android Systems

Leah Zhao; Neil Wong Hon Chan; Shanchieh Jay Yang; Roy W. Melton

Existing works have studied how to collect and analyze human usage of mobile devices, to aid in further understanding of human behavior. Typical data collection utilizes applications or background services installed on the mobile device with user permission to collect user usage data via accelerometer, call logs, location, Wi-Fi transmission, etc. through a data tainting process. Built on the existing work, this research developed a system called Panorama (Privacy-sensitive Resource Access Monitoring for Android Systems) to collect application behavior instead of user behavior. The goal is to provide the means to analyze how background services access mobile resources, and potentially to identify suspicious applications that access sensitive user information. Panorama tracks the access of mobile resources in real time and enhances the concept of taint tracking. Each identified user privacy-sensitive resource is tagged and marked for tracking. The result is a dynamic, real-time tool that monitors the process flow of applications. This paper presents the development of Panorama and a set of analysis with respect to a variety of legitimate application behaviors.


international conference on microelectronics | 1997

The teaching of VHDL in computer architecture

Tsai Chi Huang; Roy W. Melton; Philip R. Bingham; Cecil O. Alford; Farzad Ghannadian

There are problems in incorporating VHDL into the undergraduate curriculums beginning computer architecture courses. The problems relate mainly to cost arising from two factors: VHDL tool availability and proper lecture material to coincide with the course objective(s). At the Georgia Institute of Technology, pilot VHDL lecture materials have been developed to address these two issues.


international midwest symposium on circuits and systems | 2012

Low vision assistance using face detection and tracking on android smartphones

Andreas E. Savakis; Mark Stump; Grigorios Tsagkatakis; Roy W. Melton; Gary Behm; Gwen Sterns

This paper presents a low vision assistance system for individuals with blind spots in their visual field. The system identifies prominent faces in the field of view and redisplays them in regions that are visible to the user. As part of the system performance evaluation, we compare various algorithms for face detection and tracking on an Android smartphone, a netbook and a high-performance workstation representative of cloud computing. We examine processing time and energy consumption on all three platforms to determine the tradeoff between processing on a smartphone versus a cloud-desktop after compression and transmission. Our results demonstrate that Viola-Jones face detection along with Lucas-Kanade tracking achieve the best performance and efficiency.


Performance Evaluation | 2006

Predicting communication protocol performance on superscalar architectures using instruction dependency

Tsai Chi Huang; Linda M. Wills; Roy W. Melton; Cecil O. Alford

Increasing diversity in telecommunication workloads leads to greater complexity in communication protocols. This occurs as channel bandwidth rapidly increases. These factors result in larger computational loads for network processors that are increasingly turning to high performance microprocessor designs. This paper presents an analytical method for estimating the performance of instruction level parallel (ILP) processors executing network protocol processing applications. Instruction dependency information extracted while executing an application is used to calculate upper and lower bounds for throughput, measured in instructions per cycle (IPC). Results using UDP/TCP/IP applications show that the simulated IPC values fall between the analytically derived upper and lower bounds, validating the model. The analytical method is much less expensive than cycle-accurate simulation, but reveals similar throughput performance predictions. This allows the architectural design space for network superscalar processors to be explored more rapidly and comprehensively, to reveal the maximum IPC that is possible for a given application workload and the available hardware resources.


international symposium on circuits and systems | 1996

A VLSI system implementation for real-time object detection

Roy W. Melton; Tsai Chi Huang; Cecil O. Alford; L. Becker

Real-time image processing for object detection at high frame rates requires a high-performance system. Its effectiveness in object recognition over a wide range of image characteristics is proportional to its provision for varying signal processing techniques. Thus, a system designed to exhibit high performance with respect to one particular type of image and object can not be expected to prove suitable for images or objects with different characteristics. Therefore to detect different types of objects at high frame rates over a range of image characteristics, a system must offer a variety of signal processing techniques. Since general-purpose processors fall short of the performance needed in providing the necessary variety and combination of signal processing techniques, an object detection system has been designed and is being built using VLSI implementations of the signal processing techniques.


SIAM Journal on Scientific Computing | 2008

An Analysis of the Spectral Transform Operations in Climate and Weather Models

Roy W. Melton; Linda M. Wills

The spectral transform method used in climate and weather models is known to be computationally intensive. Typically accounting for more than 90% of the execution time of a serial model, it is poised to benefit from computational parallelism. Since dimensionally global transforms impact parallel performance, it is important to establish the realizable parallel efficiency of the spectral transform. To this end, this paper quantitatively characterizes the parallel characteristics of the spectral transform within an atmospheric modeling context. It comprehensively characterizes and catalogs a baseline of operations required for the spectral transform. While previous investigations of the spectral transform method have offered highly idealized analyses that are abstract and simplified in terms of orders of computational magnitude, this research provides a detailed model of the computational complexity of the spectral transform, validated by empirical results. From this validated quantitative analysis, an operational closed-form expression characterizes spectral transform performance in terms of general processor parameters and atmospheric data dimensions. These generalized statements of the computational requirements for the spectral transform can serve as a basis for exploiting parallelism.


microelectronics systems education | 1999

Teaching pipelining and concurrency using hardware description languages

Tsai Chi Huang; Sudhakar Yalamanchili; Roy W. Melton; Philip R. Bingham; Cecil O. Alford

Relating to a previous simplified VHDL processor model, a more advanced synthesized VHDL pipeline microprocessor model was developed and has been used in the second term computer architecture course offered in the School of Electrical and Computer Engineering at the Georgia Institute of Technology, USA. This paper first describes the pipeline processor model and its VHDL implementation. It then presents various implementation extensions that have been assigned and completed within a satisfactory period by participating students.


Space Programs and Technologies Conference | 1996

Application of FPA test system technology to commercial inspection/measurement systems

Roy W. Melton; Cecil O. Alford

Research conducted for the Army has recently developed an FPA (focal plane array) integrated test and evaluation system to provide a testbed for evaluating FPA characteristics and resulting object detection effectiveness. The system design offers various combinations of image processing algorithms with real–time display of raw and processed (i.e., resulting from the application of each chosen algorithm) FPA data. Because this design does not restrict itself to one particular processing scheme, it can be used for a variety of non–military applications requiring object detection within image frames. This paper investigates application of the FPA test system to commercial inspection/measurement tasks, presenting experimental results for product classification by size and color and for product grading by size, features, and quality.


Archive | 2011

Effects of GPU and CPU Loads on Performance of CUDA Applications

Maksim Bobrov; Roy W. Melton; Stanislaw P. Radziszowski; Marcin Lukowiak

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Cecil O. Alford

Georgia Institute of Technology

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Tsai Chi Huang

Georgia Institute of Technology

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Philip R. Bingham

Georgia Institute of Technology

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Joseph I. Chamdani

Georgia Tech Research Institute

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Linda M. Wills

Georgia Institute of Technology

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Muhammad Shaaban

Rochester Institute of Technology

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Shanchieh Jay Yang

Rochester Institute of Technology

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Andreas E. Savakis

Rochester Institute of Technology

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Andrew Pangborn

Rochester Institute of Technology

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Dmitri Yudanov

Rochester Institute of Technology

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