Ruiliang Xie

An Analytical Model for False Turn-On Evaluation of High-Voltage Enhancement-Mode GaN Transistor in Bridge-Leg Configuration

Compared with the state-of-the-art Si-based power devices, enhancement-mode Gallium Nitride (E-mode GaN) transistors have better figures of merit and exhibit great potential in enabling higher switching frequency, higher efficiency, and higher power density for power converters. The bridge-leg configuration circuit, consisting of a controlling switch and a synchronous switch, is a critical component in many power converters. However, owing to the low threshold voltage and fast switching speed, E-mode GaN devices are more prone to false turn-on phenomenon in bridge-leg configuration, leading to undesirable results, such as higher switching loss, circuit oscillation, and shoot through. In order to expand gate terminals safe operating margin without increasing reverse conduction loss during deadtime, negative gate voltage bias for turn-off and antiparallel diode could be applied to E-mode GaN device. In this paper, with consideration of strong nonlinearities in C–V and I–V characteristics of high-voltage (650 V) E-mode GaN transistors, analytical device models are first developed. Then, we develop an analytical circuit model that combines the circuit parameters with intrinsic characteristics of the high-voltage GaN transistor and antiparallel diode. Thus, key transient waveforms with regard to the false turn-on problem can be acquired, including displacement current and false triggering voltage pulse on gate terminal. The simulated waveforms are then verified on a testing board with GaN-based bridge-leg circuit. In contrast to piecewise switching process models and PSpice simulation, the proposed model exhibits outstanding performances. To provide design guidelines for mitigating false turn-on of GaN transistor, the impacts of different circuit parameters, along with the optimum negative gate voltage bias, are investigated based on the proposed model.

An exact discrete-time model considering dead-time nonlinearity for an H-bridge grid-connected inverter

With the development of the renewable energy, grid-connected H-bridge inverter plays a more important role than ever. However, the dead-time and the zero crossing clamping (ZCC) effect caused by dead-time can cause THD problem. As a consequence, more and more researches have focused on this issue. Most of the researches use the harmonics to replace the effect of dead-time, which ignores ZCC effect. Some other researches use the average current to distinguish the ZCC effect, which is not accurate enough. This paper analyzes the whole changing process of inductor current ripples during power cycle and a complete discrete-time model of the H-bridge grid-connected inverter with dead-time is established. On the basis of the model, the analysis of dynamic behavior is carried out, the result of which shows that the length of dead-time can cause nonlinear phenomenon and reduces the stability region of the controller parameters. Besides, this model is also useful to the nonlinearity compensation of the system.

An analytical model for false turn-on evaluation of GaN transistor in bridge-leg configuration

Gallium Nitride (GaN) transistors are especially attractive in their capability of switching at high frequencies, and enable power conversion systems with reduced size and higher efficiency. However, owing to the low threshold voltage of the commercially available enhancement-mode (E-mode) GaN devices, the devices are more prone to false turn-on phenomenon, leading to larger switching losses, circuit oscillation and even shoot-through in bridge-leg configuration. In order to enlarge the gate terminals safe operating margin without increasing the reverse conduction loss during dead-time, a negative gate voltage bias for turn-off and an anti-parallel diode can be applied to GaN transistor. In this work, to accurately evaluate the detailed turn-on characteristics of GaN transistors in bridge-leg configuration, analytical device models that count for the strong nonlinearities of devices I-V and C-V characteristics are firstly developed. Then an analytical circuit model taking into account the circuit parameters as well as the intrinsic behaviors of GaN transistor and anti-parallel diode is established. Thus, the critical transient waveforms, such as displacement currents and false triggering voltage pulse on gate terminal can be simulated. The proposed models are then verified on a testing board with GaN-based bridge-leg circuit. To provide design guidelines for suppressing false turn-on, impacts of circuit parameters are investigated based on the proposed model.

Switching transient analysis for normally-off GaN transistors with p-GaN gate in a phase-leg circuit

Gallium Nitride (GaN) transistors are emerging as promising candidates for making high-frequency, low-loss and small-size power converters. To realize normally-off, p-GaN gate technique is widely adopted in commercially available GaN-based power devices. However, owing to the distinctions in device structure, the intrinsic capacitances with regard to gate region vary from those of Si MOSFET. Besides, with drain-bias rising, the variation of gate regions net charge could make the threshold voltage of GaN transistor unstable. Thus, the switching transient waveforms of GaN transistor could be significantly influenced by the aforementioned factors, and the commonly used analysis method for Si MOSFET would not be sufficient. In this work, the threshold voltage instability is firstly analyzed, which is related to drain-to-gate voltage stress. Due to the difficulties in directly measuring the gate-related capacitances and their dynamic behaviors, a hybrid physical-behavioral modeling method is proposed, which is capable of extracting the relationship between the gate-related capacitances and their bias from the static measurements. The proposed analysis methods are then implemented on a GaN-based phase-leg circuit. Through the comparison with the experimental results and the simulated waveforms of the most advanced analysis, the proposed analysis approach exhibits outstanding performance.

Maximizing the performance of 650 V p-GaN gate HEMTs: Dynamic ron characterization and gate-drive design considerations

This paper presents a systematic characterization of a 650 V/13 A enhancement-mode GaN power transistor with p-GaN gate. Static and dynamic device characteristics are measured by taking into account of trapping induced effects such as current collapse and threshold voltage instability. Switching performance is evaluated up to 400 V, 10 A using a custom designed double-pulse test circuit. Optimal gate drive conditions are proposed to minimize the influence of adverse trapping effects on circuit performance while preventing the device from excessive gate stress. Moreover, gate drive circuit design and board layout considerations addressing the fast switching characteristics of GaN devices are also discussed.

Stability analysis of single-phase grid-connected inverter with L-filter

As an important part of the distributed power generation system, grid-connected inverter has been widely used. However, as a time-varying nonlinear system, the grid-connected inverter has complex dynamic behavior, which can cause serious stability problem. As a consequence, more and more researches have focused on this issue, most of which are limited to the stability problem caused by the variations of controller parameters, input voltage or load. This paper analyzes respectively the factors that may lead to instability such as harmonic voltage amplitude, harmonic voltage order, inductor saturation and dead-time nonlinearity. The analysis result shows that the harmonic voltage will not influence the stability of the system, but the inductor saturation and dead-time effect will cause serious stability problem in some cases. Furthermore, the design references of the controller parameters are proposed based on the result of stability analysis, which supplements the existing design references.