Ruizhi Zhang

Design of a noise-canceling differential CMOS LNA for 3.1–10.6 GHz UWB receivers

An ultra-wideband (UWB) 3.1–10.6 GHz fully differential low noise amplifier (LNA) employing the broadband noise-canceling technique is presented. With the proposed circuit topology, the noise from the input matching transistor is entirely suppressed over the full UWB band. The LNA is designed in 0.18µm CMOS technology. The simulated results show that the noise figure is 3.7–4.5 dB and the power gain is 13.4–14.1 dB in the desired UWB band, both the input and output reflection coefficients are below −10dB, and the IIP3 is −6.3dBm at 5.7 GHz. It consumes 12.5 mW from a 1.8V supply.1

A low energy ASIC for triple-chamber cardiac pacemakers with contact resistance measurement

A mixed-signal application specific integrated circuit (ASIC) is presented for triple-chamber pacemakers. To save power, a programmable stimulator composed of a 5-bit low-voltage digital-to-analog converter (DAC) and a triple-mode voltage multiplier is introduced to lower the capacitive load of the charge pump, thus reduces the charge pump driving clock frequency to 100Hz leading to significant reduction in dynamic power. According to refractory periods of the heart, a low-power control strategy is adopted in the sensing channel, in which the opamp is turned on by a sensing command and turned off automatically by a valid sensing event to reduce the average power consumption. Contact resistance measurement function based on bidirectional current injection is also integrated in the ASIC to reflect the connection status and pathological status of the patients heart. The ASIC is fabricated in a 0.35-m Bipolar-CMOS-DMOS (BCD) process with a chip area of 3.8mm3.8mm. Measurement results show that the magnitude of the stimulus pulse can be programmed from 0.1 to 7.5V with 0.1-V step. Almost linear heart resistance measuring is achieved in the resistance range of 2504000. The average current consumption is 4A under typical pacing algorithms from a 2.8-V power supply.

A mixed-signal ASIC for triple-chamber cardiac pacemakers with heart resistance measurement

This paper presents a mixed-signal ASIC for triple-chamber pacemakers. The ASIC performs four major functionalities: 1) sensing of heartbeat signals; 2) measuring the heart resistance of three chambers independently to diagnose the attachment status of the electrodes and provide additional information about the pathological status of the patients heart; 3) generating stimulus pulses with programmable magnitude and pulse width; 4) receiving commands and configuration data from MCU, and transferring register data to MCU through the SPI interface. The ASIC is fabricated in a 0.35-μm BCD technology with a chip area of 3.8×3.8 mm2. Measurement results show that the magnitude of the stimulus pulses can be programmed from 0. 1 to 7.4 V with 0.1-V step. Almost linear heart resistance measuring is achieved in the resistance range of 250 to 4000 Q. Average current consumption is 4 μA from a 2.8-V supply.

A resistor-less bandgap reference with improved PTAT generator for ultra-low-power LSIs

A resistor-less bandgap reference (BGR) for ultra-low power large-scale integrations (LSIs) is proposed in this paper. The BGR consists of a nano-ampere current reference circuit, a complementary-to-absolute-temperature (CTAT) voltage generator based on a diode connected MOSFET operating in subthreshold region, and a proportional-to-absolute-temperature (PTAT) voltage generator. A new topology that combines two mechanisms to generate PTAT voltage is proposed for the first stage of the PTAT generator, which can achieve higher slope in the voltage-temperature characteristics. Therefore, only 3 sub-stages are required in the PTAT generator, and both power dissipation and chip area can be reduced. The BGR is designed in a 0.35-μm CMOS process. Simulated results show that the BGR achieves a 1.1-V reference voltage with best temperature coefficient of 35 ppm/°C, while consuming only 40-nA under a 3.3 V power supply.

A low-power G m -R-C image rejection filter for complex low-IF receiver

In this paper, a 1^st-order G<inf>m</inf>-R-C complex filter cell for image rejection in low-IF receivers is proposed. The cell adopts low-power fully differential G<inf>m</inf>-cells with RC load to perform low-pass filtering for the input I/Q signals. Frequency translation is realized by two additional differential G<inf>m</inf> cells through directly cross-adding relevant currents. Based on the proposed 1^st-order cell, a 4^th-order Butterworth complex filter with center frequency at 300 KHz and bandwidth of 160 KHz is designed in 0.18 µm CMOS technology. Simulated results show that the filter achieves an image rejection ratio of 62 dB, an in-band SFDR of 58.9 dB, a pass-band gain of 18 dB, and an input referred noise of 19.4 µV<inf>rms</inf>, while consuming only 593 µA from a 2.7 V supply.

A high-efficiency charge pump in BCD process for implantable medical devices

This paper presents a high-efficiency charge pump circuit composed of cascaded cross-coupled voltage doublers implemented in an isolated bipolar-CMOS-DMOS (BCD) technology for implantable medical devices. Taking advantage of the transistor structures in the isolated BCD process, the leakage currents caused by the parasitic PNP transistors in the cross-coupled PMOS serial switches are eliminated by simply connecting the inside substrate terminal to the isolation terminal of each PMOS transistor. The simple circuit structure leads to small parasitic capacitance in the voltage doubler, which in turn ensures high efficiency of the overall charge pump. The proposed charge pump with 5 cascaded voltage doublers is fabricated in a 0.35-μm isolated BCD process. Measurement results with 2-V power supply, 1-MHz driving clock frequency and 40-μA current load show that an efficiency of 72.6% is achieved, and the output voltage can be pumped to about 11.5 V at zero load current. The chip area of the charge pump is 1.6 × 0.35 mm2.

Joint Background Calibration of Gain and Timing Mismatch Errors with Low Hardware Cost for Time-Interleaved ADCs

A joint background calibration scheme is proposed for the gain and timing mismatch errors in time-interleaved analogue-to-digital converts (TI ADCs). Mixed-signal calibration is adopted for timing mismatch without using correlators or multi-tap digital filters, while the gain mismatch is estimated and calibrated all digitally based on the moving average of the derivative for each channels output. Therefore, the influence of offset mismatch on the estimation accuracy of the gain error can be eliminated completely. To reduce hardware cost as much as possible, most of the arithmetic blocks are reused for gain and timing mismatch estimation. Behavioural simulation with a 12 bit, 2 GSPS two-channel TI ADC and measurement results from a commercial 12 bit 3.6 GSPS two-channel TI ADC show that the proposed joint calibration scheme can effectively correct the gain and timing mismatch errors.

An inductive wireless telemetry circuit with OOK modulation for implantable cardiac pacemakers

An inductive wireless telemetry circuit for implantable cardiac pacemakers is presented in this paper. An internal coil in the titanium case transmits the detected cardiac data into the coil of the outside programmer. The configuration data and the commands from the programmer are sent to the pacemaker through the same pair of coils to save volume of the system. In order to realize reliable and low-power communication through the titanium housing, OOK modulation with a carrier frequency of 128 KHz is adopted for the system. The internal demodulator is realized simply with a diode-based rectifier, while the external demodulation circuit is realized with a front-end active band-pass filter and a DFF-based low-pass filter. Measurement from a prototype system with discrete components shows that a raw data-rate of 8 Kb/s is realized with a maximum distance of 10cm. The average operation power consumption are 575μA and 3.2 mA for the internal and external circuit, respectively.

Nonlinearity analysis of the boosted bucket brigade device for high-speed charge-domain ADCs

The charge-domain analog-to-digital converter (ADC) based on boosted bucket-brigade devices (BBD) is an opamp-less pipelined ADC architecture, which can provide high conversion speed with very low power consumption compared with traditional pipelined ADC architectures. However, the charge transfer characteristics of the MOS BBD exhibits severe nonlinearity, which poses a hard limit on the linearity performances of the pipelined ADC. In this paper, the influences of the circuit parameters of the BBD on its linearity performance are analyzed theoretically and verified by simulation. The results of analysis and simulation show that the nonlinear response of boosting amplifier has the most serious impact on the linearity of the BBD. Based on the analysis results of the paper, relatively higher linearity of charge-domain ADCs can be obtained by choosing reasonable circuit parameters for the BBDs used in the ADC.

A 3.1–10.6GHz frequency synthesizer for MB-OFDM UWB transceivers

A frequency synthesizer capable of generating all the 14 sub-band carrier frequencies in 3.1~10.6GHz band for multiband OFDM ultra-wideband (MB-OFDM UWB) transceivers is proposed. It is composed of a phase-locked loop (PLL), two singlesideband (SSB) mixers, and two multiplexers (MUXs). Switched-cascode architecture with switched LC tanks is adopted in the multiplexers to ensure fast switching. A buffer with series peaking is employed for the output SSB mixer to enlarge its bandwidth. The synthesizer is designed in TSMC 0.18μm CMOS technology. The simulated switching time between each sub-band is approximately 3ns. The current consumption excluding that of the PLL is 25mA under 1.8V power supply.