Rune Erlend Jensen

π -Cipher: Authenticated Encryption for Big Data

In today’s world of big data and rapidly increasing telecommunications, using secure cryptographic primitives that are parallelizable and incremental is becoming ever more important design goal. π-Cipher is parallel, incremental, nonce based authenticated encryption cipher with associated data. It is designed with the special purpose of providing confidentiality and integrity for big data in transit or at rest. It has, as an option, a secret part of the nonce which provides noncemisuse resistance. The design involves operations of several solid cryptographic concepts such as the Encrypt-then-MAC principle, the XOR MAC scheme and the two-pass sponge construction. It contains parameters that can provide the functionality of tweakable block ciphers for authenticated encryption of data at rest. The security of the cipher relies on the core permutation function based on ARX (Addition, Rotation and XOR) operations. π-Cipher offers several security levels ranging from 96 to 256 bits.

Organizing Visual Data in Structured Layout by Maximizing Similarity-Proximity Correlation

The goal of this work is to organize visual data into structured layouts such that proximity reflects similarity. The problem is formulated as maximizing the correlation between the dissimilarities among the data and their placement distances in the structured layouts. An efficient greedy-based coarse-to-fine algorithm is proposed to compute near optimal data placements. The qualities of such placements are verified using an enumeration-based algorithm that is capable of computing the exact solution for small-scale problems. Results on different datasets show that data items with low dissimilarity being placed near one another whereas those with high dissimilarity are placed apart. This facilitates users to understand the relations among the data items and to locate the desired ones during the browsing.

Measurement Bias from Address Aliasing

In this paper, we identify address aliasing as an important underlying mechanism causing measurement bias on modern Intel microarchitectures. By analyzing hardware performance counters, we show how bias arises from two external factors:size of environment variables, and characteristics of dynamically linked heap allocators. We demonstrate ways to deal with this type of bias, through runtime detection and correction of aliasing conditions. For heap allocators, we show that common implementations tend to give worst case alignment by default, favoring page alignment for large allocations. The performance impact of aliased memory accesses can be significant, causing up to a 2x performance degradation in already optimized code. Our results can enable new optimization strategies to account for this phenomenon.