Runze Han

Oxide-based RRAM switching mechanism: A new ion-transport-recombination model

This paper presents a unified physical model to elucidate the resistive switching behavior of metal-oxide-based resistive random access memory (RRAM) devices using the ion-transport-recombination model. In this model, the rupture of conductive filaments is caused by recombination of oxygen ions and electron-low-occupied oxygen vacancies. The transport equations of interstitial oxygen ions in the oxide matrix are introduced to quantitatively investigate the reset speed and other properties such as uniformity, endurance, and reset current. The proposed mechanism was verified by experiments.

A unified physical model of switching behavior in oxide-based RRAM

Excellent bipolar resistive switching (RS) behavior was achieved in TiN/ZnO/Pt resistive random access memory (RRAM) devices. A unified physical model based on electrons hopping transport among oxygen vacancies along the conductive filaments (CFs) is proposed to elucidate the RS behavior in the RRAM devices. In the unified physical model, a new reset mechanism due to the depletion of electrons in oxygen vacancies and the recovery of electron-depleted oxygen vacancies (VO +) with non-lattice oxygen ions (O2-) is proposed and identified.

A Novel Operation Scheme for Oxide-Based Resistive-Switching Memory Devices to Achieve Controlled Switching Behaviors

A new operation scheme on oxide-based resistive-switching devices [resistive random access memory (RRAM)] is proposed to improve the controllability of switching processes in order to achieve an improved memory performance. The improved device-to-device and cycle-to-cycle uniformity, reduced RESET current, and adjustable RHRS/RLRS ratio are demonstrated in the HfOx-based RRAM devices by using the new operation scheme, indicating the validity of the new operation scheme. The physical mechanism accounting for the new operation scheme effect is discussed.

Monte Carlo simulation of Schottky contact with direct tunnelling model

In this paper, we have presented a practical direct tunnelling model, which can be applied in the Monte Carlo simulation of the Schottky contact. In this model, the thermionic emission and the tunnelling effect of the Schottky barrier are included. In order to verify the validity of this model, we have implemented it in the Monte Carlo simulator to simulate the characteristics of the Schottky barrier diode. An agreement has been obtained between the simulation results and the measurements. Besides, we apply this model to study the performance of the n-channel Schottky barrier MOSFET (SB-MOSFET), in which the doped source/drain of the conventional MOSFET is replaced by metal silicide. We find that the low barrier at the source will induce high drive current in the on state, and at the same time reduce the on/off ratio. In addition, decreasing the metal silicide source/drain contact areas will improve the performance of the SB-MOSFET. By using this model, the simulation of the n-channel SB-MOSFET will be helpful in designing the parameters of these kinds of devices.

Mechanism of positive-bias temperature instability in sub-1-nm TaN/HfN/HfO/sub 2/ gate stack with low preexisting traps

In this letter, the positive-bias temperature instability (PBTI) characteristics of a TaN/HfN/HfO/sub 2/ gate stack with an equivalent oxide thickness (EOT) of 0.95 nm and low preexisting traps are studied. The negligible PBTI at room temperature, the so-called turn-around phenomenon, and the negative shifts of the threshold voltage (V/sub t/) are observed. A modified reaction-diffusion (R-D) model, which is based on the electric stress induced defect generation (ESIDG) mechanism, is proposed to explain the above-mentioned PBTI characteristics. In this modified R-D model, PBTI is attributed to the electron-induced breaking of Si-O bonds at interfacial layer (IL) between HfO/sub 2/ and Si substrate and the diffusion/drift of oxygen ions (O/sup -/) from Si-O bonds into HfO/sub 2/ layer under positive-bias temperature stressing. The ESIDG mechanism is responsible for the breaking of Si-O bonds. The measured activation energy (E/sub a/) is consistent with the one predicted by the ESIDG mechanism.

Reconfigurable Nonvolatile Logic Operations in Resistance Switching Crossbar Array for Large-Scale Circuits

Resistance switching (RS) devices have potential to offer computing and memory function. A new computer unit is built of RS array, where processing and storing of information occur on same devices. Resistance states stored in devices located in arbitrary positions of RS array can be performed various nonvolatile logic operations. Logic functions can be reconfigured by altering trigger signals.

Scalability and Reliability Characteristics of CVD HfO2 Gate Dielectrics with HfN Electrodes for Advanced CMOS Applications

Metal-oxide-semiconductor (MOS) devices using a thermally robust HfN/HfO 2 gate stack were fabricated. The equivalent oxide thickness of HfN/HfO 2 gate stack has been aggressively scaled down to 0.75 and 0.95 nm for MOS capacitors and metal-oxide-semiconductor field effect transistors, respectively, after a thermal budget required by the conventional complementary metal-oxide-semiconductor gate-first process. The reliability issues such as time-dependent dielectric breakdown (TDDB) and bias temperature instability (BTI) of the HfN/HfO 2 devices are studied. The stress electric-field-dependent TDDB characteristics are demonstrated and explained by a model taking into account the high energetic carrier trapping in the HfO 2 and at the HfO 2 /Si interfacial layer. The polarity dependent BTI characteristics are observed which can be explained by a generalized reaction-diffusion model. These intrinsic reliability characteristics are correlated with the low pre-existing charge traps in HfO 2 gate stack resulting from a high temperature postdeposition annealing of the HfN/HfO 2 gate stack.

Improved electrical and reliability Characteristics of HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm EOT fabricated using a gate-first Process

By using a high-temperature gate-first process, HfN--HfO/sub 2/-gated nMOSFET with 0.95-nm equivalent oxide thickness (EOT) was fabricated. The excellent device characteristics such as the sub-1-nm EOT, high electron effective mobility (peak value /spl sim/232 cm/sup 2//V/spl middot/s) and robust electrical stability under a positive constant voltage stress were achieved. These improved device performances achieved in the sub-1-nm HfN--HfO/sub 2/-gated nMOSFETs could be attributed to the low interfacial and bulk traps charge density of HfO/sub 2/ layer due to the 950/spl deg/C high-temperature source/drain activation annealing process after deposition of the HfN--HfO/sub 2/ gate stack.

Triple-gate FinFETs with Fin-thickness Optimization to Reduce the Impact of Fin Line Edge Roughness

Shimeng Yu, Yuning Zhao, Gang Du, Jinfeng Kang, Ruqi Han, and Xiaoyan Liu* Institute of Microelectronics, Peking University, Beijing 100871, P. R. China Shenzhen Graduate School, Peking University, Guangdong 518055, P. R. China *xyliu@ime.pku.edu.cn Introduction: Intra-die fluctuations in the nanoscale CMOS technology emerge due to intrinsic parameter fluctuations induced by line edge roughness (LER) [1]. LER can cause the random deviation of the line edge from its ideal pattern and it does not reduce with scaling down of line width [2]. FinFET is a promising candidate that can be applied into sub-30nm technology with good ability to suppress the short channel effects (SCEs) [3]. However, to reduce fluctuations of FinFETs performance is still imperative [4] and the strongest fluctuations are introduced by the fin LER [5]. As the fin is conventionally designed less than one third of the channel length to suppress SCEs [6], it imposes a big challenge on the lithography and etching. Here we propose to relax the fin-thickness constraints in order to reduce the influence of intra-die fluctuations. Through our 3-D simulation, we suggest using triple-gate FinFETs with optimized fin-thickness to minimize the fin LER effects, meanwhile to suppress SCEs under a tolerable degree. Device Structure and Simulation Method: Fig. 1 shows the device structure of triple-gate FinFETs with fin LER. The geometrical and doping parameters used in simulation are listed in Table 1. Fin roughness is generated by a Fourier analysis of the Gaussian autocorrelation function introduced in our earlier work [7]. Fig. 2 is schematic of the flow to generate the random sequence. The properties of FinFETs we consider include threshold voltage Vt,lin at Vds=50mV and Vt,sat at Vds=1V; the value of the drain induced barrier lower effect (DIBL) defined as (Vt,lin-Vt,sat)/ Vds; drive current Ion and leakage current Ioff. Hundreds of 20nm double-gate (DG) and triple-gate (TG) FinFETs with different fin-thickness (Tsi) are simulated in 3-D by ISE-TCAD tools [8]. Since LER does not reduce with scaling down of line width [2], we assume all the samples have the same rms amplitude (1nm) of fin LER in spite of different Tsi. Fisrtly, FinFETs with smooth line edge (referred as ideal) are evaluated. Then FinFETs with fin LER (referred as rough) are simulated to investigate their properties’ shifts (evaluated by average value Avg) and fluctuations (evaluated by standard deviation ). In order to achieve statistical stability, all the simulations have an ensemble size of 100. Quantum effect is taken into account by density-gradient method. Results and Discussion: Fig. 3 shows that with the increase of Tsi, ideal FinFETs’ Vt,lin decreases almost linearly while Vt,sat drops dramatically. The outcome of SCEs is unavoidable because the gate controllability of the front and back gates reduces when fin is widened. However, TG structure performs better than DG structure in the suppression of the SCEs due to the top gate’s control over channel. Fig. 4 plots ideal FinFETs’ DIBL value as a function of Tsi, showing TG devices’ advantage to suppress SCEs when fin is widened. Fig. 5 shows that with the increase of Tsi, ideal FinFETs’ Ion rises almost linearly and Ioff rises almost exponentially. It is noticed that TG devices’ benefits such as larger drive current and smaller leakage current do not appear until Tsi exceeds half the channel length (10nm). Fig. 6 shows that fin LER contributes to a remarkable increase of threshold voltage, and the thinner the fin is, the more Vt,lin shifts. This is because the quasi-continuous conduction band splits into a series of discrete sub-bands due to quantum confinement effect. The thinner the fin is, the more notable this effect becomes. Fig. 6 also shows with the same Tsi, Vt,lin’s shifts are less remarkable in TG devices than in DG devices. Thus, TG FinFETs with wider fin present a potential ability to reduce fin LER effects. However, widening the fin should be treated carefully, for it may exacerbate the SCEs as shown in Fig. 7. Fortunately, DIBL does not rise as aggressively as expected in TG devices, noting that in Fig. 7 rough FinFETs with TG structure have a lower DIBL than that of ideal FinFETs. Another drawback of widening fin is the exponentially increase of leakage current as shown in Fig. 8. However, the leakage current of rough FinFETs does not rise as aggressively as expected in ideal FinFETs because fin LER contributes to a significant increase of threshold voltage. Additionally, it can be seen in Fig. 8 that when fin is thin, TG devices even have a larger Ioff than DG devices, because at this region Ioff is dominated by gate leakage current rather than sub-threshold leakage current, and TG devices have a relatively larger area of gate. TG devices’ superiority in lowering leakage current does not appear until the fin is wide enough (eg. 20nm). Fig. 9 shows that with the increase of Tsi, the fluctuations of Vt,lin drop almost linearly. Also TG devices present better consistency of threshold voltage under the influence of fin LER. Fig. 10 shows that with the increase of Tsi, the fluctuations of DIBL drop dramatically. Although the absolute value of DIBL increases when the fin is widened, the variation is weakened. The similar phenomenon can be observed in Fig. 11, which shows that with the increase of Tsi, the fluctuations of leakage current drop dramatically. Moreover, in Fig. 10 and Fig. 11, TG devices present superiority to DG devices in the suppression of the SCEs such as the increase of DIBL and leakage current. In summary, widening the fin inevitably brings about SCEs. However, using TG devices instead of DG devices can achieve better resistance to SCEs because of the top gate’s control over the channel. What makes more sense is that widening the fin can significantly reduce the shifts and fluctuations of device performance caused by fin LER effects. From our simulation above, we suggest relaxing fin-thickness constraints from less than one third of the channel length to half or even equal to the channel length. With the help of TG structure, FinFETs with optimized fin-thickness can reduce the influence of fin LER meanwhile suppress SCEs under a tolerable degree. Conclusion: By 3-D statistical simulation, we investigate the effects brought by widening the fin of ideal FinFETs with smooth line edge and rough FinFETs with fin LER. The results show that the benefits of widening fin to reduce shifts and fluctuations caused by fin LER outweigh the detriment of possibly enhanced SCEs. So we propose to relax the fin-thickness constraints to achieve better resistance to fin LER effects. In the meantime, we propose to use triple-gate FinFETs to replace the conventional double-gate FinFETs to help suppress SCEs after fin is widened. Our simulation provides guidelines for designing FinFETs device to reduce intra-die fluctuations. Acknowledgement: This work is supported by NKBRP2006CB302705 and NSFC 60736030. Reference: [1] A. Asenov, et al, IEEE Trans. Electron Devices, Vol. 50, No. 9, pp. 1837-1852, Sep. 2003. [2] P. Oldiges, et al, in Proc. SISPAD, 2000, pp. 131–134. [3] B. Yu, et al, in IEDM Tech. Dig., 2002, pp. 251–254. [4] A. Dixit, et al, in IEDM Tech. Dig., 2006, pp. 709–712. [5] E. Baravelli, et al, IEEE Trans. Electron Devices, Vol. 54, No. 9, pp. 2466–2474, Sep. 2007. [6] G. Pei, et al, IEEE Trans. Electron Devices, Vol. 49, No. 8, pp. 1411-1419, Aug. 2002. [7] S. Yu, et al, in Silicon Nanoelectronics Workshop, 2008. [8] ISE-TCAD tools from Integrated System Engineering (ISE). Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, Tsukuba, 2008,

A New Model for Two-Dimensional Electrical-Field-Dependent

The 2-D electrical-field-dependent hot-hole-related negative-bias temperature instability (HH-NBTI) behaviors of pMOSFETs with 1.7-nm decoupled-plasma-nitridation oxynitride dielectrics are investigated. The lateral-channel electric-field-induced turnaround HH-NBTI degradation that is associated with the enhanced breaking effect of the interfacial Si-H bonds at the Si interface is demonstrated. For the first time, the lateral-electric-field-dependent activation energy of ≡ Si- H bond dissociation is presented. A new model taking into account the 2-D electric field effects is proposed to depict the HH-NBTI behaviors related to the lateral- and vertical-channel electric fields. The proposed model is verified by the experimental data.