Ruoyu Xu

Electric-Field Intrabody Communication Channel Modeling With Finite-Element Method

Electric-field intrabody communication (EF-IBC) is a promising new scheme for the data exchange among wearable biomedical sensors. It uses the body as the signal transmission media. Compared with existing body area network (BAN) schemes, EF-IBC can achieve higher data rate with less transmission power. Until now, the detailed EF-IBC channel mechanism is not well understood. In this work, finite-element method (FEM) is utilized for the first time to investigate the EF-IBC channel. A circuit-coupled FEM model is established for the EF-IBC channel. The FEM model is extensively verified by experimental measurements. The new physical model enables the revelation of characteristics and effects of different components in the EF-IBC channel. The FEM investigation finds that the capacitive return path is critical to the characteristics of the EF-IBC channel. Parameters of the capacitive return path are quantitatively measured. The investigation also finds that the body plays an important role to the return path capacitance. The forward body path can be well modeled by a cascade of π-shaped circuits. Based on the FEM model of the EF-IBC channel, a simplified circuit model is derived to provide an efficient tool for the transceiver design.

Digitally Calibrated 768-kS/s 10-b Minimum-Size SAR ADC Array With Dithering

Array sensors require a high-performance analog-to-digital converter (ADC) array with small area and low power. Successive-approximation register (SAR) ADC has good potential for ADC array due to its simple analog circuits. However, SAR ADCs with 10-b resolution and higher normally need a large capacitor array due to the stringent matching requirement. The large capacitor array also limits the ADC dynamic performance. The capacitor mismatch has been compensated by analog calibration techniques. In this work, a novel digital calibration method is developed for SAR ADC based on dithering. With dithering, weights of most significant bit (MSB) capacitors can be measured accurately so that very small capacitors can be used in the SAR ADC due to the relaxed matching requirement. A modified bit-cycling procedure is developed to avoid the code gaps caused by capacitor dithering. This calibration technique requires no analog calibration overhead and simple digital decoders. The technique is implemented in an ADC array design including 256 SAR ADCs for a high-speed CMOS imaging sensor in a 0.18-μm CMOS process. The 10-b SAR ADC is designed with the minimum capacitor array size in the process. A single SAR ADC only occupies 15 μm × 710 μm. Sampling at 768 kS/s, peak DNL and peak INL of the original ADCs averaged across the array are 0.82 least significant bit (LSB) and 3.85 LSB, respectively. For a signal close to the Nyquist frequency, original ADCs have 7.96-b average ENOB. After calibration with dithering, ADCs have 0.55-LSB peak DNL and 0.77-LSB peak INL averaged across the array. The average ENOB improves to 9.83 b. Compared with the benchmark 10-b SAR ADCs, this design is the most area-efficient design. In this work, the calibration decoders are implemented off-chip. With a sample-and-hold amplifier, the calibration method can run in the background.

Equation Environment Coupling and Interference on the Electric-Field Intrabody Communication Channel

Wearableand implantable medical sensors have been investigated continuously in recent years to provide better diagnostics and monitoring for personal health care. Much attention has been drawn to the establishment of the ubiquitous body area network (BAN) to reliably connect the body sensors and collect the sensor data in real time. Electric-held intrabody communication (EF-IBC) is a promising physical link technology for the body area network. Compared to existing wireless technologies, EF-IBC hts the body characteristics better and is able to achieve higher data rate with less transmission power. EF-IBC relies on the parasitic capacitive coupling between the transmitter and the receiver to close the signal circuit loop. With this parasitic coupling, EF-IBC links can be influenced by the environment. However until now, there is lack of systematic research on various environment coupling effects to the EF-IBC channel. In this paper, environment effects on the EF-IBC channel are comprehensively studied. The interference from the nearby EF-IBC channel is investigated for the first time to gain useful insights into the establishment of the BAN with EF-IBC. The FEM model is also established to explain the mechanism of the capacitive return path.

A 12-bit 20 MS/s 56.3 mW Pipelined ADC With Interpolation-Based Nonlinear Calibration

The linearity of a high-resolution pipelined analog- to-digital converter (ADC) is mainly limited by the capacitor mismatch and the finite operational amplifier (OPAMP) gain in the multiplying-digital-to-analog converter (MDAC). Therefore, high resolution pipelined ADCs usually require high-gain OPAMP and large capacitors, which causes large ADC power. In recent years, various nonlinear calibration techniques have been developed to compensate both linear and nonlinear error from MDCAs so that low-power MDACs with small capacitors and low-gain OPAMP can be used. Hence, the ADC power can be greatly reduced. This paper introduces a novel interpolation- based digital self-calibration architecture for pipelined ADC. Compared to previous techniques, the new architecture is free of adaptation. Hence, long convergence is not needed. The complexity of the digital processor is also considerably lower. The new architecture does not use backend ADC to measure MDACs. Hence, it is free of the accumulation of measurement error, which leads to more accurate calibration. A prototype ADC with the calibration architecture is fabricated in a 0.35 3.3 V CMOS process. The ADC samples at 20 MS/s. The calibration improves the ADC DNL and INL from 1.47 LSB and 7.85 LSB to 0.2 LSB and 0.27 LSB. For a 590 kHz sinusoidal signal, the calibration improves the ADC signal-to-noise-distortion ratio(SNDR) and spurious-free dynamic range (SFDR) from 41.3 dB and 52.1 dB to 72.5 dB and 84.4 dB respectively. The 11.8-ENOB 20 MS/s ADC consumes 56.3 mW power with 3.3 V supply. The 0.78 pJ/step figure-of-merit (FOM) is low for designs in 0.35 CMOS processes. At the Nyquist frequency, SNDR of the calibrated ADC drops 8 dB due to the slow settling of the first pipeline stage.

Characterization and analysis of intra-body communication channel

In this work, the experiment setup of EF-IBC is studied. An effective setup is developed to preserve the parasitic return path in EF-IBC. Characteristics of every component in an EF-IBC system are measured or derived through a combination of experiments. The measured EF-IBC channel shows a bandpass profile with a center frequency around 42MHz. The channel bandpass profile is mainly determined by the capacitive parasitic return path and the capacitive PCB leakage path. Below 100MHz, the body appears to be a uniform attenuator with about 15dB loss at the distance of 15cm between TX and RX. The channel characteristics are recombined by all the components, and match well with the direct measurement results, which verifies the decomposition method.

A 1500 fps Highly Sensitive 256

High-speed CMOS imaging sensors (CIS) normally have low sensitivity because of the large integration capacitance. They also have high noise because pixel circuits cannot implement correlated double sampling (CDS) to remove the pixel reset noise. For applications, such as micro-computed tomography (micro-CT), this is a major limitation. In this work, we developed a technique to achieve high sensitivity and low noise for high-speed CIS. To maximize the sensitivity, we designed a new capacitive transimpedance amplifier (CTIA) pixel with a tiny metal-oxide-metal capacitor. The pixel circuit also implements CDS. As a result, the temporal noise is greatly reduced, and the sensitivity improves dramatically. To compensate the mismatch of small integration capacitors across the pixel array, an on-chip calibration scheme with in-pixel circuits is developed. Fully differential column circuits are designed to suppress the power supply injection in the large array of high-speed column circuits. A successive-approximation analog-to-digital (SAR ADC) is designed to achieve 10-bit resolution and to fit in the 15-μm column pitch. For testing modes, column circuits are configured into a two-step ADC to provide 13-bit dynamic range. The 256 × 256 CIS design is fabricated in a 0.18-μm CMOS process. The imager samples up to 1500 fps. The pixel integration capacitor is 0.7 fF, which enables 68.5 V/lux · s sensitivity under the white illumination. The CIS temporal noise is 13.6e-. This sensitivity and noise performances are much better than previous high-speed CIS benchmark designs. Running at 1500 fps, the CIS can capture recognizable images with illumination down to 1 lux. The on-chip calibration suppresses the fixed-pattern noise lower than 0.52%. The prototype chip consumes 390 mW of power.

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Machine vision requires CMOS image sensors (CISs) with high frame rate, short exposure time, and fine spatial resolution. Recently, capacitive transimpedance amplifier (CTIA) is used in the high-speed pixel circuit to achieve high sensitivity by expediting the charge transfer from the photodiode to a tiny integration capacitor ( CINT). Existing CTIA pixel designs have large pixel sizes due to the multiple sampling capacitors and switches for global shutter and CDS, which unfavorably limits the spatial resolution. In this paper, we present a 400 fps CIS design with 640 × 480 pixel array for machine vision. With simplified pixel circuits, the new sensor has a CTIA pixel size of 8.7 × 8.22 μm2, which is the smallest in the category. The pixel implements a new multi-layer MOM capacitor with good uniformity as the tiny CINT, which achieves high sensitivity (36.5 V/lux·s) without calibration. Pixel-wise CDS is implemented in this global-shutter CIS to minimize the pixel noise. The pixel signals are quantized by 640 column processing slices with 12 bit resolution at 411 kS/s. The size of the column SAR ADC is minimized with a simple calibration technique. The CIS is fabricated in a 0.18 μm mixed-signal CMOS process. The temporal noise is 15.6 erms-. With the new MOM capacitor, FPN of the CIS is 0.55% without calibration. The new pixel design achieves the highest sensitivity per unit area.

256 CMOS Imaging Sensor With In-Pixel Calibration

The electric-field (EF) intra-body communication (IBC) is a promising data transmission method for high-speed low-power biomedical sensors. A good model of the EF-IBC channel is needed for better understanding the signal propagation principle and more efficient IBC transceiver design. Although various effective models have been developed for the waveguide IBC channel, the EF-IBC channel has only been modeled by empirical distributed RC network. In this paper, a circuit-coupled finite-element-method (FEM) model is established to analyze the EF-IBC channel. A multi-layer FEM model is developed for the human forearm. The parasitic effects of the probe PCBs and the return path are modeled as circuit elements. The circuit-coupled FEM model is simulated in ANSYS. Simulation results show that the model agrees well with the EF-IBC measurements. The circuit-coupled FEM model provides useful insights into the EF-IBC mechanism.

A 1/2.5 inch VGA 400 fps CMOS Image Sensor With High Sensitivity for Machine Vision

Intra-body communication (IBC) uses the conductive human body as the communication channel for data exchange. As the bio-sensor research is moving towards portable, wearable and implantable designs, IBC has significant potential applications for personal health care. Previous IBC research mainly focused on the electromagnetic (EM) IBC scheme, which resulted in low data rate (kbps). In this paper, we systematically studied the electric field (EF) IBC scheme, which enables 10Mbps data rate. The human body channel is thoroughly measured with attenuation, noise and distortion for the IBC application. High speed EF IBC links are tested with various modulation schemes. The minimum transmission power of different links is measured.

Circuit-coupled FEM analysis of the electric-field type intra-body communication channel

The linearity of a pipeline analog-to-digital converter (ADC) is mainly limited by capacitor mismatch and finite operational amplifier (OPAMP) gain, which cause large power and design difficulty in modern nanometer CMOS processes for high-resolution pipeline ADCs. It is a trend of developing digital calibration techniques to compensate the analog error in pipeline stages. This paper systematically introduces a novel interpolation-based digital calibration architecture to compensate both linear and nonlinear errors from pipeline stages. The new method does not require convergence. The effect of calibration error is analyzed in detail in this paper. A prototype 20-MS/s pipeline ADC is fabricated in a 0.35-μm 3.3-V CMOS process. For 12-b resolution, the digital calibration improves the ADC differential nonlinearity and integral nonlinearity from 1.47 LSB and 7.85 LSB to 0.2 LSB and 0.27 LSB. For a 590-kHz sinusoidal signal, the calibration improves the ADC signal-to-noise-distortion ratio and spurious-free dynamic range from 41.3 dB and 52.1 dB to 72.5 dB and 84.4 dB, respectively. With the new calibration technique, low-gain OPAMPs and small capacitors are used in the pipeline. The designed ADC has 0.78-pJ/step figure of merit (FOM), which is among the lowest reported FOMs for high-resolution pipeline ADC designs. The new architecture requires an accurate calibration ADC (CalADC) and two digital decoders. CalADC is implemented on-chip with 6.5% die area and 8.9% power. The decoders are synthesized to have 912 gates and consume 23.4% ADC power.