Russell W. Duren

FPGA implementation of particle swarm optimization for inversion of large neural networks

Particle swarm inversion of large neural networks is a computationally intensive process. By the implementing a modified particle swarm optimizer and neural network in reconfigurable hardware, many of the computations can be preformed simultaneously, significantly reducing compilation time compared to a conventional computer.

Real-Time Neural Network Inversion on the SRC-6e Reconfigurable Computer

Implementation of real-time neural network inversion on the SRC-6e, a computer that uses multiple field-programmable gate arrays (FPGAs) as reconfigurable computing elements, is examined using a sonar application as a specific case study. A feedforward multilayer perceptron neural network is used to estimate the performance of the sonar system (Jung , 2001). A particle swarm algorithm uses the trained network to perform a search for the control parameters required to optimize the output performance of the sonar system in the presence of imposed environmental constraints (Fox , 2002). The particle swarm optimization (PSO) requires repetitive queries of the neural network. Alternatives for implementing neural networks and particle swarm algorithms in reconfigurable hardware are contrasted. The final implementation provides nearly two orders of magnitude of speed increase over a state-of-the-art personal computer (PC), providing a real-time solution

Challenges of Remote FPGA Configuration for Space Applications

There are many unique challenges associated with providing remote access to space experimental payloads. The limited bandwidth to the space craft, the inability to physically monitor and probe the payload, and the management of access time for various researchers working on the project all compound to create a challenging work environment. The configurable fault tolerant processor (CFTP) project aims to alleviate many of the difficulties associated with remote payload operation. We have made use of modular FPGA design, which allows us to transfer only small application modules rather than full configuration files. This dramatically reduces the bandwidth required to upload new applications as we discover new experiments for the CFTP after launch. Another unique aspect of the CFTP project is the collaborative effort in its development. We must manage access time for universities and research institutions across the country for running experiments on the CFTP, downloading CFTP documents, and analyzing telemetry after launch

Options For Upgrading Legacy Avionics Systems

This paper examines a comprehensive set of options for upgrading legacy avionics systems in tactical aircraft. The options have been developed as part of study involving the avionics system of a current military aircraft Multiple options are considered ranging from minor changes to the legacy system to complete replacement of computers and communications buses with commercial off-the-shelf (COTS) hardware and new software. The pros and cons of each potential solution are described and guidelines are given for choosing the appropriate solution for a given program. The results of this study may be used when evaluating upgrade options for a wide range of embedded computer applications.

A new neural network architecture for rotationally invariant object recognition

Introduces a novel neural network architecture for rotationally invariant object recognition. Second-order neurons are used in combination with polar sampling to obtain invariance without incurring excessive network size. Multiple experiments are presented, demonstrating that incorporation of a variable range of rotational invariance results in improved performance over previous methods. The proposed architecture is computationally efficient and avoids the use of subsampling and the resulting loss of recognition accuracy. It has the additional benefit that the range of rotational invariance can be easily adapted to specific applications where full rotational invariance is not appropriate.<<ETX>>

Performance enhancement of avionics systems

Many studies on managing obsolescence and refreshing technology concentrate on replacing hardware to improve the performance of legacy systems. In contrast, this authors research has concentrated on the development of methods that can significantly enhance the performance of legacy systems while requiring few or no hardware modifications. If hardware replacement is allowed, these methods can be leveraged to further improve the upgraded systems. The methods can be characterized either as algorithmic or architectural methods. Algorithmic methods include techniques such as new data compression routines. A previous paper by this author and a fellow researcher presented data compression routines that are suitable for implementation on legacy MIL-STD-1553 data buses. As expected, these routines were shown to increase the communication throughput. What may be less obvious is that they also increased the time available to perform computation. Architectural techniques include repartitioning of software functions and/or communications to free system resources. This presents these and other methods for increasing the performance of legacy avionics systems. The same techniques can also be applied to improve the design of new systems.

A comparison of FPGA and DSP development environments and performance for acoustic array processing

This paper compares the development effort and performance of a field programmable gate array (FPGA)-based implementation of a signal processing solution with that of a traditional digital signal processor (DSP) implementation. An acoustic array processing task was selected as a typical problem. A simple metric is proposed to compare the design effort.

Application of Data Compression to the MIL-STD-1553 Data Bus

This paper examines multiple data compression algorithms that improve the effective bandwidth of systems using the MIL-STD-1553 data bus. The algorithms are evaluated using data captured from F/A-18 C/D aircraft flights and simulations. Compression ratios of 5 to 1 and greater are achieved using algorithms that are suitable for implementation on legacy processors. It is demonstrated that the time required to compress and decompress the data can be more than offset by the savings in data transmission time. System implementation issues and the effects of data transmission errors are also discussed.

Electronic Warfare Digital Signal Processinig On COTS Computer Systems With Reconfigurable Architectures

Commercial off-the-shelf computer systems with reconfigurable architectures have recentlybecomeavailable.Someofthesemachineshavearchitectures,features,andsoftware development environments that seem to make them useful for digital signal processing, especiallyinelectronicwarfareandradarsignalprocessingapplications.Thispaperdescribes experiments to evaluate the architecture, features, software development environment, and performance of one such computer, the SRC Computers model SRC-6e, using an electronic warfare signal processing application.

Algorithmic and architectural methods for performance enhancement of avionics systems

Many studies on managing obsolescence and refreshing technology concentrate on replacing hardware to improve the performance of legacy systems. In contrast, the authors research has concentrated on the development of methods that can significantly enhance the performance of legacy systems while requiring few or no hardware modifications. If hardware replacement is allowed, these methods can be leveraged to further improve the upgraded systems. The methods can be characterized either as algorithmic or architectural methods. Algorithmic methods include techniques such as new data compression routines. A previous paper by the author and a fellow researcher has presented data compression routines that are suitable for implementation on legacy MIL-STD-1553 data buses. As expected, these routines where shown to increase the communication throughput. What may be less obvious is that they also increased the time available to perform computation. Architectural techniques include repartitioning of software functions and/or communications to free system resources. This paper presents these and other methods for increasing the performance of legacy avionics systems. The same techniques can also be applied to improve the design of new systems.