Ruzica Jevtic

Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors

Integrating multiple power converters on-chip improves energy efficiency of manycore architectures. Switched-capacitor (SC) dc-dc converters are compatible with conventional CMOS processes, but traditional implementations suffer from limited conversion efficiency. We propose a dynamic voltage and frequency scaling scheme with SC converters that achieves high converter efficiency by allowing the output voltage to ripple and having the processor core frequency track the ripple. Minimum core energy is achieved by hopping between different converter modes and tuning body-bias voltages. A multicore processor model based on a 28-nm technology shows conversion efficiencies of 90% along with over 25% improvement in the overall chip energy efficiency.

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI

This work demonstrates a RISC-V vector microprocessor implemented in 28nm FDSOI with fully-integrated non-interleaved switched-capacitor DCDC (SC-DCDC) converters and adaptive clocking that generates four on-chip voltages between 0.5V and 1V using only 1.0V core and 1.8V IO voltage inputs. The design pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

Power Estimation of Embedded Multiplier Blocks in FPGAs

The use of embedded multiplier blocks has become a norm in DSP applications due to their high performance and low power consumption. However, as their implementation details in commercial field-programmable gate arrays are not available to users, and the power estimates given by the tested low-level tool are not accurate enough to validate high-level models, the work on power estimation of these blocks is very limited. We present a dynamic power estimation methodology for the embedded multipliers in Xilinx Virtex-II Pro chips. The methodology is an adaptation of an existing power estimation method for lookup-table-based components and uses information about the type of architecture of the embedded block. The power model is characterized and verified by on-board measurements and is ready for integration with high-level power optimization techniques. The experimental results show that the average accuracy of the model is higher than the average accuracy of the low-level commercial tool.

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC–DC Converters in 28 nm FDSOI

This work demonstrates a RISC-V vector microprocessor implemented in 28 nm FDSOI with fully integrated simultaneous-switching switched-capacitor DC-DC (SC DC-DC) converters and adaptive clocking that generates four on-chip voltages between 0.45 and 1 V using only 1.0 V core and 1.8 V IO voltage inputs. The converters achieve high efficiency at the system level by switching simultaneously to avoid charge-sharing losses and by using an adaptive clock to maximize performance for the resulting voltage ripple. Details about the implementation of the DC-DC switches, DC-DC controller, and adaptive clock are provided, and the sources of conversion loss are analyzed based on measured results. This system pushes the capabilities of dynamic voltage scaling by enabling fast transitions (20 ns), simple packaging (no off-chip passives), low area overhead (16%), high conversion efficiency (80%-86%), and high energy efficiency (26.2 DP GFLOPS/W) for mobile devices.

A complete dynamic power estimation model for data-paths in FPGA DSP designs

A complete model for estimating power consumption in DSP-oriented designs implemented in FPGAs is presented. The model consists of three submodels. One is used for power estimation of the global routing employed for interconnections between the components. It depends on their mutual distance and shape. The other estimates clock power and depends on the estimated design area. The remaining model is used for both local interconnect and logic power estimation of the components. It is based on the analytical computation of the switching activity produced inside the component in the presence of correlated inputs. The complete model has been characterized and verified by on-board power measurements, instead of using low-level estimation tools which often lack the required accuracy. The results show that the mean relative error of each individual submodel always lies within 10% of the physical measurements, while the complete model has a mean relative error of only 12%.

Multiple-Input Relay Design for More Compact Implementation of Digital Logic Circuits

Multiple-input relays are proposed to enable more compact implementation of digital logic circuits, and the first functional prototypes are presented. A relay with three equally sized input electrodes is demonstrated to perform various three-input logic functions, with a delay that can be well predicted by a lumped-parameter model. Relays with differently sized input electrodes can be used to perform more complex functions. A flash-type analog-to-digital converter is presented as one example.

Technology Variability From a Design Perspective

Increased variability in semiconductor process technology and devices requires added margins in the design to guarantee the desired yield. Variability is characterized with respect to the distribution of its components, its spatial and temporal characteristics and its impact on specific circuit topologies. Approaches to variability characterization and modeling for digital logic and SRAM are analyzed in this paper. Transistor arrays and ring oscillator arrays are designed to isolate specific systematic and random variability components in the design. Distributions of SRAM design margins are measured by using padded-out cells and observing minimum array operating voltages. Correlations between various components of variability are essential for adding appropriate margins to the design.

An Agile Approach to Building RISC-V Microprocessors

The final phase of CMOS technology scaling provides continued increases in already vast transistor counts, but only minimal improvements in energy efficiency, thus requiring innovation in circuits and architectures. However, even huge teams are struggling to complete large, complex designs on schedule using traditional rigid development flows. This article presents an agile hardware development methodology, which the authors adopted for 11 RISC-V microprocessor tape-outs on modern 28-nm and 45-nm CMOS processes in the past five years. The authors discuss how this approach enabled small teams to build energy-efficient, cost-effective, and industry-competitive high-performance microprocessors in a matter of months. Their agile methodology relies on rapid iterative improvement of fabricatable prototypes using hardware generators written in Chisel, a new hardware description language embedded in a modern programming language. The parameterized generators construct highly customized systems based on the free, open, and extensible RISC-V platform. The authors present a case study of one such prototype featuring a RISC-V vector microprocessor integrated with a switched-capacitor DC-DC converter alongside an adaptive clock generator in a 28-nm, fully depleted silicon-on-insulator process.

Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits

Power models are at the heart of high-level estimation methods used for industrial power evaluation of FPGA-based electronic designs. In this paper, probabilistic power estimation models of binary divider IP cores implemented in reconfigurable logic are presented. The models are ready for use at the algorithmic and RTL levels of the design flow and are simulation-independent, thus resulting in fast estimation times. The only parameters the model needs are the bit-widths of the operator inputs and their signal statistics: mean values, variances and autocorrelation coefficients. Based on these parameters and taking into account the particular logic structure of the binary divider cores, analytical probabilistic formulas are used to calculate the overall switching activity in the circuits-the main cause of dynamic power consumption. Estimates are compared with both real on-board measurements and estimates from the simulation-based tool XPower from Xilinx. Results show that the mean relative estimation errors are within 10% of on-board measurements or low-level estimates, and the average time to obtain power estimates using the proposed models is only 135 ms.

Switching activity models for power estimation in FPGA multipliers

This paper presents a novel high-level analytical approach to estimate logic power consumption of multipliers implemented in FPGAs in the presence of glitching and correlation. The proposed methodology is based on: 1) an analytical model for the switching activity of the component, and 2) a structural analysis of the FPGA implementation of the component. The complete model is parameterized in terms of complexity factors such as word-lengths and signal statistics of the operands. It also accounts for the glitching introduced by the component. Compared to the other power estimation methods, the number of circuit simulations needed for characterizing the power model of the component is highly reduced. The accuracy of the model is within 10% of low-level power estimates given by the tool XPower and it achieves better performance than other proposed high-level approaches.