Ryan J. Leduc

Hierarchical interface-based supervisory control-part II: parallel case

In this paper, we present a hierarchical method that decomposes a system into two subsystems, and restricts the interaction of the subsystems by means of an interface. We present definitions for two types of interfaces [represented as discrete-event systems (DESs)], and define a set of interface consistency properties that can be used to verify if a DES is nonblocking and controllable. Each clause of the definitions can be verified using only one of the two subsystems; thus, the complete system model never needs to be constructed, offering potentially significant savings in computational effort. Additionally, the development of clean interfaces facilitates reuse of the component subsystems. Finally, we examine a simple example to illustrate the method.

Hierarchical interface-based supervisory control of a flexible manufacturing system

Flexible manufacturing systems have long been touted as an application area for supervisory control theory. Unfortunately, due to the typical exponential growth of state space with the number of interacting subsystems, concurrent systems such as manufacturing applications have, for the most part, remained beyond the reach of existing supervisory control theory tools. This paper demonstrates how, by imposing a hierarchical, modular, interface-based architecture on the system, significant gains can be made in the size of applications that can be handled by supervisory control theory. We first review hierarchical interface-based supervisory control, providing the theory necessary to motivate the creation of well-defined automata-based interfaces between components. This architecture permits the verification of global safety (controllability) and nonblocking properties to be decomposed into a set of local checks, each of which only involves an individual component subsystem and its interface automata. The paper then provides a detailed description of how the theory can be applied to the design and verification of a flexible manufacturing system work cell. The work cell model is based on the Atelier Intere/spl acute/tablissement de Productique flexible manufacturing workcell, a system that has been previously studied in the literature with limited success.

Symbolic Synthesis and Verification of Hierarchical Interface-based Supervisory Control

Hierarchical interface-based supervisory control (HISC) decomposes a discrete-event system (DES) into a high-level subsystem which communicates with n ges 1 low-level subsystems, through separate interfaces which restrict the interaction of the subsystems. It provides a set of local conditions that can be used to verify global conditions such as nonblocking and controllability. The current HISC verification and synthesis algorithms are based upon explicit state and transition listings which limit the size of a given level to about 107 states when 1GB of memory is used. In this paper, we extend the HISC approach by introducing a set of predicate based fixed point operators that allow us to do a per level synthesis to construct for each level a maximally permissive supervisor that satisfies the corresponding HISC conditions. We prove that these fixpoint operators compute the required level-wise supremal languages. We then present algorithms that implement the fixpoint operators. Based on these algorithms, a symbolic implementation is briefly discussed which can be implemented using binary decision diagrams. We also discuss a method to implement our synthesized supervisors in a more compact manner. A large manufacturing system example (worst case state space on the order of 1030) extended from the ALP example is briefly discussed. The example showed that we can now handle a given level with a statespace as large as 10 15 states, using less than 160MB of memory. This represents a significant improvement in the size of systems that can be handled by the HISC approach. A software tool for synthesis and verification of HISC systems using our approach was also developed

Hierarchical interface-based supervisory control: serial case

We present a hierarchical method that decomposes a system into two subsystems, and restricts the interaction of the subsystems by means of an interface. We present a definition for an interface, and define a set of interface consistency properties that can be used to verify if a discrete-event system is nonblocking and controllable. Each clause of the definition can be verified using only one of the two subsystems; thus the complete system model never needs to be constructed, offering significant savings in computational effort. Additionally, the development of clean interfaces facilitates re-use of the component subsystems.

Synthesis Method for Hierarchical Interface-Based Supervisory Control

Hierarchical Interface-based Supervisory Control (HISC) decomposes a discrete-event system (DES) into a high-level subsystem which communicates with n ges 1 low- level subsystems, through separate interfaces which restrict the interaction of the subsystems. It provides a set of local conditions that can be used to verify global conditions such as nonblocking and controllability. As each clause of the definition can be verified using a single subsystem, the complete system model never needs to be stored in memory, offering potentially significant savings in computational resources. Currently, a designer must create the supervisors himself and then verify that they satisfy the HISC conditions. In this paper, we develop a synthesis method that can take advantage of the HISC structure. We replace the supervisor for each level by a corresponding specification DES. We then do a per level synthesis to construct for each level a maximally permissive supervisor that satisfies the corresponding HISC conditions. We define a set of language based fixpoint operators and show that they compute the required level-wise supremal languages. We then discuss the complexity of the algorithms that we have constructed that implement the fixpoint operators and show that they potentially offer significant improvement over the monolithic approach. A large manufacturing system example (estimated worst case statespace on the order of 1022) extended from the AIP example is discussed. A software tool for synthesis and verification of HISC systems using our approach was also developed.

Synthesis Method for Hierarchical Interface-based Supervisory Control

Hierarchical Interface-based Supervisory Control (HISC) decomposes a discrete-event system (DES) into a high-level subsystem which communicates with n ges 1 low- level subsystems, through separate interfaces which restrict the interaction of the subsystems. It provides a set of local conditions that can be used to verify global conditions such as nonblocking and controllability. As each clause of the definition can be verified using a single subsystem, the complete system model never needs to be stored in memory, offering potentially significant savings in computational resources. Currently, a designer must create the supervisors himself and then verify that they satisfy the HISC conditions. In this paper, we develop a synthesis method that can take advantage of the HISC structure. We replace the supervisor for each level by a corresponding specification DES. We then do a per level synthesis to construct for each level a maximally permissive supervisor that satisfies the corresponding HISC conditions. We define a set of language based fixpoint operators and show that they compute the required level-wise supremal languages. We then discuss the complexity of the algorithms that we have constructed that implement the fixpoint operators and show that they potentially offer significant improvement over the monolithic approach. A large manufacturing system example (estimated worst case statespace on the order of 1022) extended from the AIP example is discussed. A software tool for synthesis and verification of HISC systems using our approach was also developed.

Discrete event systems modeling and control of a manufacturing testbed

In this paper, we describe the manufacturing testbed we have built to investigate the implementation of RW supervisors on programmable logic controllers (PLC). We discuss the modeling of the testbed and the design of its controllers. Finally, we present several theorems for verifying controllability and nonblocking on large systems.

A compositional approach for verifying generalised nonblocking

This paper proposes a compositional approach to verify the generalised nonblocking property of discrete-event systems. Generalised nonblocking is introduced in [1] to overcome weaknesses of the standard nonblocking check in discrete-event systems and increase the scope of liveness properties that can be handled. This paper addresses the question of how generalised nonblocking can be verified efficiently. The explicit construction of the complete state space is avoided by first composing and simplifying individual components in ways that preserve generalised nonblocking. The paper extends and generalises previous results about compositional verification of standard nonblocking and lists a new set of computationally feasible abstraction rules for standard and generalised nonblocking.

Compositional Nonblocking Verification Using Generalized Nonblocking Abstractions

This paper proposes a method for compositional verification of the standard and generalized nonblocking properties of large discrete event systems. The method is efficient as it avoids the explicit construction of the complete state space by considering and simplifying individual subsystems before they are composed further. Simplification is done using a set of abstraction rules preserving generalized nonblocking equivalence, which are shown to be correct and computationally feasible. Experimental results demonstrate the suitability of the method to verify several large-scale discrete event systems models both for standard and generalized nonblocking.

Sampled-data supervisory control

This paper focuses on the issues related to the implementation of theoretical timed discrete-event systems (TDES) supervisors, and the concurrency and timing delay issues involved. In particular, we examine issues related to implementing TDES as sampled-data (SD) controllers. An SD controller is driven by a periodic clock and sees the system as a series of inputs and outputs. On each clock edge (tick event), it samples its inputs, changes state, and updates its outputs. We identify a set of existing TDES properties that will be useful to our work, but not sufficient. We extend the TDES controllability definition to a new definition, SD controllability, which captures several new properties that will be useful in dealing with concurrency issues, as well as make it easier to translate a TDES supervisor into an SD controller. We present controllability and non-blocking results for SD controllers.