Ryo Kawahara

Verification of embedded system's specification using collaborative simulation of SysML and simulink models

The authors propose an extension of SysML which enables description of continuous-time behavior. The authors also develop its execution tool integrated on Eclipse-based platform by exploiting co-simulation of SysML and MATLAB / Simulink. To demonstrate the effectiveness of the tool and the extension to SysML in verifying specifications of an embedded system, we create a sample model and analyze its execution results by checking constraints under a test case.

Coarse-grained simulation method for performance evaluation a of shared memory system

We propose a coarse-grained simulation method which takes the effect of memory access contention into account. The method can be used for the evaluation of the execution time of an application program during the system architecture design in an early phase of development. In this phase, information about memory access timings is usually not available. Our method uses a statistical approximation of the memory access timings to estimate their influences on the execution time. We report a preliminary verification of our simulation method by comparing it with an experimental result from an image processing application on a dual-core PC. We find an error of the order of 3 percents on the execution time.

A modeling method by eliminating execution traces for performance evaluation

This paper describes a system-level modeling method in UML for performance evaluation of embedded systems. The core technology of this modeling method is reverse modeling based on dynamic analysis. A case study of real MFPs (multifunction peripherals/printers) is presented in this paper to evaluate the modeling method.

A model-based method for evaluating embedded system performance by abstraction of execution traces

This paper describes a model-based method to evaluate performance of embedded systems. The core technology of this modeling method is reverse modeling based on dynamic analysis of the existing systems. A case study of real MFPs (multifunction peripherals/printers) is presented in this paper to evaluate the modeling method.

MVA-Based Probabilistic Model of Shared Memory with a Round Robin Arbiter for Predicting Performance with Heterogeneous Workload

Memory access contention can be a cause of performance problems and should be assessed at early stages of development. We devised a probabilistic model of shared memory for performance estimation. The calculation time is polynomial in the number of processors. The model is applicable for the region of high and heterogeneous bandwidth utilization. A round-robin arbiter is modeled using Mean Value Analysis MVA based approximations and incorporating non-linear dependence to the bandwidth utilization. To evaluate our model, estimated execution time is compared with the measured execution time of benchmark programs with memory access contention. We find a maximum error of 4.2% for the round-robin arbitration when we compensate for the burstiness of accesses.