Ryo Minami

A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c

This paper presents a 60-GHz direct-conversion transceiver using 60-GHz quadrature oscillators. The transceiver has been fabricated in a standard 65-nm CMOS process. It in cludes a receiver with a 17.3-dB conversion gain and less than 8.0-dB noise figure, a transmitter with a 18.3-dB conversion gain, a 9.5-dBm output 1 dB compression point, a 10.9-dBm saturation output power and 8.8-% power added efficiency. The 60-GHz frequency synthesizer is implemented by a combination of a 20-GHz PLL and a 60-GHz quadrature injection-locked oscillator, which achieves a phase noise of -95 dBc/Hz@l MHz-offset at 60 GHz. The transceiver realizes IEEE802.15.3c full-rate wireless communication for all 16QAM/8PSK/QPSK/BPSK modes, and the communication distances with the full data rate using 2.16-GHz bandwidth, measured with an antenna built in the package, are 2.7-m (BPSK/QPSK) and 0.2-m (8PSK/16QAM). The measured maximum data rates are 8 Gb/s in QPSK mode and 11 Gb/s in 16QAM mode over a 5 cm wireless link within a bit error rate (BER) of <;10-3. The transceiver consumes 186 mW from a 1.2-V supply voltage while transmitting and 106 mW from 1.0-V supply voltage while receiving. Both transmitter and receiver are driven by a 20-GHz PLL, which consumes 66 mW, including output buffer, from a 1.2-V supply voltage.

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry

This paper presents a 60-GHz direct-conversion RF front-end and baseband transceiver including analog and digital circuitry for PHY functions. The 65-nm CMOS front-end consumes 319 and 223 mW in transmitting and receiving mode, respectively. It is capable of more than 7-Gb/s 16QAM wireless communication for every channel of the 60-GHz standards, which can be extended up to 10 Gb/s. The 40-nm CMOS baseband including analog, digital, and I/O consumes 196 and 427 mW for 16QAM in transmitting and receiving modes, respectively. In the analog baseband, a 5-b 2304-MS/s ADC consumes 12 mW, and a 6-b 3456-MS/s DAC consumes 11 mW. In the digital baseband integrating all PHY functions, a (1440, 1344) LDPC decoder consumes 74 mW with the low energy efficiency of 11.8 pJ/b. The entire system including both RF and BB using a 6-dBi antenna built in the organic package can transmit 3.1 Gb/s over 1.8 m in QPSK and 6.3 Gb/s over 0.05 m in 16QAM.

A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry

This paper presents a 60 GHz direct-conversion front-end and baseband transceiver, including analog and digital circuitry for the PHY functions. The 65 nm CMOS front-end consumes 319 mW and 223 mW in transmitting and receiving mode, respectively, and is capable of more than 7 Gb/s 16QAM wireless communication for every channel of the 60 GHz standards. The 40 nm CMOS baseband incorporating LDPC consumes 196 mW and 398 mW for 16QAM in transmitting and receiving mode, respectively. The entire system, using a 6dBi antenna built in an organic package, can transmit 3.1Gb/s over 1.8 m in QPSK and 6.3 Gb/s over 0.05 m in 16QAM.

20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding

This paper presents a 64-QAM 60GHz CMOS transceiver, which achieves a TX-to-RX EVM of -26.3dB and can transmit 10.56Gb/s in all four channels defined in IEEE802.11ad/WiGig. By using a 4-bonded channel, 28.16Gb/s can be transmitted in 16QAM. The front-end consumes 251mW and 220mW from a 1.2-V supply in transmitting and receiving mode, respectively. Figure 20.3.1 shows the 60GHz direct-conversion front-end design. The transmitter consists of a 6-stage PA, differential preamplifiers, I/Q passive mixers and a quadrature injection-locked oscillator (QILO). The receiver consists of a 4-stage LNA, differential amplifiers, I/Q double-balanced mixers, a QILO, and baseband amplifiers. A direct-conversion architecture is employed for both TX and RX because of wide-bandwidth capability [1]. The LO consists of the 60GHz QILO and a 20GHz PLL. The 60GHz QILO works as a frequency tripler with the integrated 20GHz PLL. It can generate 7 carrier frequencies with a 36/40MHz reference, 58.32GHz(ch.1), 60.48GHz(ch.2), 62.64GHz(ch.3), and 64.80GHz(ch.4) defined in IEEE802.11ad/WiGig, 59.40GHz(ch.1-2), 61.56GHz(ch.2-3), and 63.72GHz(ch.3-4) for the channel bonding.

A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS

This paper presents a 16QAM direct-conversion transceiver in 65nm CMOS, which is capable of 60-GHz wireless standards. The capacitive cross-coupling neutralization contributes a high common-mode rejection and a high reverse isolation, and a fully-balanced mixer can improve the error vector magnitude due to the reduced local leakage. The maximum data rates with an antenna built in a package are 10Gb/s in QPSK mode and 16Gb/s in 16QAM mode and the transmitter and the receiver consume 181mW and 138 mW, respectively.

A digitally-calibrated 20-Gb/s 60-GHz direct-conversion transceiver in 65-nm CMOS

This paper presents a digitally-calibrated 60-GHz direct-conversion transceiver. To improve the error vector magnitude (EVM) performance over the wide bandwidth, a digital calibration technique is applied. The 60-GHz transceiver implemented by 65 nm CMOS achieves the maximum data rates of 20 Gb/s in 16QAM mode. The transmitter and receiver consume 351 mW and 238 mW from 1.2 V supply, respectively. As a 60-GHz transceiver, the best Tx-to-Rx EVM performance of -26.2 dB is achieved for 16QAM 7Gb/s data rate.

A 0.7 V-to-1.0V 10.1 dBm-to-13.2 dBm 60-GHz power amplifier using digitally-assisted LDO considering HCI issues

A 60-GHz power amplifier (PA) with consideration of hot-carrier-induced (HCI) degradation is presented. The supply voltage of the last stage of the PA (VPA) is dynamically controlled by an on-chip digitally-assisted low drop-out voltage regulator (LDO) to alleviate HCI effects. The PA is fabricated in a standard 65-nm CMOS process with a core area of 0.21 mm2, which provides a saturation power of 10.1 dBm to 13.2 dBm with a peak power-added efficiency (PAE) of 8.1% to 15.0% for PA varying from 0.7V to 1.0V at 60 GHz, respectively.

A 60GHz power amplifier using high common-mode rejection technique

This paper proposes the method of realization of high common-mode rejection ratio(CMRR) at 60 GHz. High CMRR can compensate the differential mismatch. In the proposed method, virtual ground for differential-mode and LC peaking for common-mode are utilized. To confirm the effect of this technique, the 2-stage differential power amplifier is fabricated in a 65nm CMOS process. It achieves a CMRR of 26 dB, a power gain of 12.1 dB, a peak PAE of 11.1%, a Psat of 9.0 dBm, a power consumption of 45.8mW from a 1.0V power supply.

A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOS

This paper presents a 60-GHz direct-conversion transceiver using 60-GHz quadrature oscillators. The 65 nm CMOS transceiver realizes the IEEE802.15.3c full-rate wireless communication for every 16QAM/8PSK/QPSK/BPSK mode. The maximum data rates with an antenna built in a package are 8 Gbps in QPSK mode and 11 Gbps in 16QAM mode within a BER of <;10-3. The transceiver consumes 186 mW while transmitting, and 106 mW while receiving. The PLL also consumes 66 mW.

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay

This paper presents 64-quadrature amplitude modulation (QAM) 60-GHz CMOS transceivers with four-channel bonding capability, which can be categorized into a one-stream transceiver and a two-stream frequency-interleaved (FI) transceiver. The transceivers are both fabricated in a standard 65-nm CMOS technology. For the proposed one-stream transceiver, the TX-to-RX error vector magnitude (EVM) is less than −23.9 dB for 64-QAM wireless communication in all four channels defined in the IEEE 802.11ad/WiGig. The maximum communication distance with the full rate can reach 0.13 m for 64 QAM, 0.8 m for 16 QAM, and 2.6 m for QPSK using 14-dBi horn antennas. A data rate of 28.16 Gb/s is achieved in 16 QAM by four-channel bonding. The transmitter, receiver, and phase-locked loop consume 186, 155, and 64 mW, respectively. The core area of the transceiver is 3.9 mm2. For the proposed two-stream FI transceiver, four-channel bonding in 64 QAM is realized with a data rate of 42.24 Gb/s and an EVM of less than −23 dB. The front end consumes 544 mW in transmitting mode and 432 mW in receiving mode from a 1.2-V supply. The core area of the transceiver is 7.2 mm2.