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Featured researches published by Ryoichi Nagayoshi.


international solid-state circuits conference | 1994

A 2/3-inch 2.0 M-pixel M-FIT CCD with a single channel HCCD for HDTV camera

Y. Toyoda; Keijirou Itakura; Toshihide Nobusada; Y. Saitoh; N. Kokusenya; Ryoichi Nagayoshi; H. Tanaka; Masayoshi Ozaki; M. Sugawara; K. Mitani; Y. Fujita

HDTV technology is now entering the practical stage. Efforts have been devoted to realizing the hand-held HDTV camera using three 2/3-inch 2.0M-pixel CCDs. However, the data reported so far showed poor performance because of the limited space of the unit pixel. This high performance 2/3-inch 2.0M-pixel CCD with a single HCCD employs M-FIT architecture. The CCD exhibits saturation current of 580nA, sensitivity of 44nA/lx, smear level of -100dB, and amplitude response at 800TV lines of 60%.<<ETX>>


international solid-state circuits conference | 1993

A multiple frame-interline-transfer (M-FIT) CCD for progressive-scan camera systems

Keijirou Itakura; Toshihide Nobusada; Y. Toyoda; Y. Saitoh; N. Kokusenya; Ryoichi Nagayoshi; Masayoshi Ozaki

A progressive scan CCD (charge coupled device) that features multiple-frame interline transfer (M-FIT) operation is described. This 2/3-inch 500-k (948*486)-pixel M-FIT CCD is implemented on the basis of a conventional 2poly-Si process, and has a 16:9 aspect ratio (switchable to 4:3), an 80-dB dynamic range, and 25-nA/1*sensitivity. A schematic diagram of an experimental device developed for the next-generation widescreen TV camera system is shown. Measured photoconversion characteristics are shown together with those for a conventional progressive scan CCD. A reproduced image of a resolution chart in which 480 TV-line resolution is achieved by the progressive scan is also shown.<<ETX>>


international solid-state circuits conference | 1998

A 1 mm 50 K-pixel IT CCD image sensor for miniature camera system

Keijirou Itakura; Toshihide Nobusada; N. Kokusenya; Ryoichi Nagayoshi; Masayoshi Ozaki

A 1 mm 50 k-pixel interline CCD features a 4/spl times/4 /spl mu/m/sup 2/ pixel, integration of a Vsub adjust circuit and a packageless assembly of a chip-provided microlens. The chip size and the assembled device outer sizes are 1.1 (H)/spl times/1.34 (V)mm/sup 2/ and 1.2 (H)/spl times/1.5 (V)mm/sup 2/ respectively. The 4/spl times/4 /spl mu/m/sup 2/-Pixel has image quality equivalent to that of conventional 5/spl times/5 /spl mu/m/sup 2/ pixel. Channel narrowing is important in design with small pixel size, because narrowed channel causes reduction of handling charge in the vertical CCD. A low-temperature oxidation process minimizes channel narrowing caused by lateral diffusion of boron. The thickness of the transfer gate oxide is reduced to 80%, which also results in an increase of handling charge. Tne creation of the p-well and n-type region of the photodiode (PD) are by high-energy ion implantation, making the isolation length between VCCD and PD shorter than that with the conventional method. Owing to the above techniques, VCCD with 0.8pm channel width has 2.0/spl times/10/sup 4/ electron/pixel handling charge.


22nd International Congress on High-Speed Photography and Photonics | 1997

2/3-in. 2-M-pixel CCD with progressive scan capability

Masayuki Sugawara; Ryoichi Nagayoshi; Yoshihiro Fujita; Keijirou Itakura

High-definition charge-coupled device (CCD) image sensors developed as image pickup devices for television systems so far have adopted interlaced scanning. But, it is preferable for users to have the alternative of interlaced or progressive scanning in developing applications that use image input technology for purposes other than television. This paper describes a novel CCD configuration called advanced frame interline transfer (A-FIT) that can be applied to either interlaced or progressive scanning environments by merely modifying the drive pulse of the same device. What distinguishes the A-FIT CCD imager is that, while it retains the same number of stages in the imaging area register as a CCD for interlaced scanning, it features a new storage area structure enabling the imager to support both interlaced and progressive scanning. Specifically, the vertical CCD register in the storage area is vertically partitioned down the middle to form two registers. This layout permits charges of odd-numbered lines or even- numbered lines to be shifted separately. And when the charges are transferred to the horizontal readout register, interlaced scanning results if the charges are mixed and progressive scanning results if the even and odd lines are alternated or interleaved. A prototype 2/3-inch 2-million- pixel CCD pickup was fabricated based on the novel A-FIT layout, and subjected to testing to verify its capability to perform both interlaced and progressive scanning. It was found that the CCD imagers vertical resolution was superior in progressive scan mode compared to when the chip was operated in interlaced scan mode.


Archive | 2003

Solid-state image sensing device and camera using the same

Ryoichi Nagayoshi; Toshiya Fujii; Tsuyoshi Hasuka; Akiyoshi Kohno; Shinichi Tashiro; Keijiro Itakura


Archive | 2006

Method for driving solid-state imaging apparatus and solid-state imaging apparatus

Tsuyoshi Hasuka; Ryoichi Nagayoshi; Keijirou Itakura; Izumi Shimizu; Yoshiaki Kato


Archive | 2005

Solid-state image sensor, solid-state image sensing apparatus, camera, and method

Toshiya Fujii; Ryoichi Nagayoshi; Akiyoshi Kohno; Shinichi Tashiro


Archive | 2009

Solid-state image sensor, solid-state image sensing apparatus, camera, and method for controlling a solid-state image sensor

Toshiya Fujii; Ryoichi Nagayoshi; Akiyoshi Kohno; Shinichi Tashiro


Archive | 2005

Semiconductor device and camera using same

Ryoichi Nagayoshi


Archive | 2005

Source follower amplifier device and camera using same

Ryoichi Nagayoshi; Nobuhiko Mutoh

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