Ryusuke Kawano

A 10-Gb/s (1.25 Gb/s/spl times/8)4/spl times/2 0.25-/spl mu/m CMOS/SIMOX ATM switch based on scalable distributed arbitration

This paper presents the design and implementation of a scalable asynchronous transfer mode switch. We fabricated a 10-Gb/s 4/spl times/2 switch large-scale integration (LSI) that uses a new distributed contention control technique that allows the switch LSI to be expanded. The developed contention control is executed in a distributed manner at each switch LSI, and the contention control time does not depend on the number of connected switch LSIs. To increase the LSI throughput and reduce the power consumption, we used 0.25-/spl mu/m CMOS/SIMOX (separation by implanted oxygen) technology, which enables us to make 221 pseudo-emitter-coupled-logic I/O pins with 1.25-Gb/s throughput. In addition, power consumption of 7 W is achieved by operating the CMOS/SIMOX gates at -2.0 V. This consumption is 36% less than that of bulk CMOS gates (11 W) at the same speed at -2.5 V. Using these switch LSIs, an 8/spl times/8 switching multichip module with 80-Gb/s throughput was fabricated with a compact size.

Merging advanced electronic and optical WDM technologies for 640-Gbit/s ATM switching system

An experimental 640-Gbit/s ATM switching system is described. The switching system is scalable and quasi-nonblocking. It uses hardware self-rearrangement in a three-stage network. Hardware implementation results for the switching system is presented. The switching system is fabricated using advanced 0.25 /spl mu/m CMOS devices, high-density multi-chip-module (MCM) technologies, and optical wavelength division multiplexed (WDM) interconnection technologies. A scalable 80-Gbit/s switching module is fabricated combined with a newly developed scalable-distributed-arbitration technique, and a WDM interconnection system that connects all 80-Gbit/s switching modules is developed. Using these components: an experimental 640-Gbit/s switching system is partially constructed. It can be applied to realize future broadband ATM networks.

640-Gb/s high-speed ATM switching system based on 0.25-/spl mu/m CMOS, MCM-C, and optical WDM interconnection

A 640-Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM-C, 0.25-/spl mu/m CMOS, and optical wavelength-division-multiplexing (WDM) interconnection is fabricated for future broadband backbone networks. A 40-layer, 160/spl times/114 mm ceramic MCM forms the basic ATM switch module with 80-Gb/s throughput. It consists of 8 advanced 0.25-/spl mu/m CMOS LSIs and 32 I/O bipolar LSIs. The MCM has a 7-layer high-speed signal line structure having 50-/spl Omega/ strip lines, high-speed signal lines, and 33 power supply layers formed using 50-/spl mu/m thick ceramic layers to achieve high capacity. A uniquely structured closed-loop-type liquid cooling system for the MCM is used to cope with its high power dissipation of 230 W. A three-stage ATM switch is made using the optical WDM interconnection between high-performance MCMs. For WDM interconnection, newly developed compact 10-Gb/s, 8-WDM optical transmitter and receiver modules are used. These modules are each only 80/spl times/120/spl times/20 mm and dissipate 9.65 W and 22.5 W, respectively. They have a special chassis for cooling, which contains high-performance heat-conductive plates and micro-fans. An optical WDM router based on an arrayed waveguide router is used for mesh interconnection of boards. The optical WDM interconnect has 640-Gb/s throughput and simple interconnection.

A 100-Gb/s throughput ATM switch MCM with a 320-channel parallel optical I/O interface

For an ATM switch system, we have developed a 100-Gb/s input/output (I/O) throughput optical I/O interface ATM switch multichip module (MCM) that has 320-ch optical I/O ports. This MCM is fabricated using ceramic (MCM-C) technology and very-small highly-parallel O/E and E/O optical converters. It uses 0.25-/spl mu/m complementary metal oxide semiconductors (CMOS) ATM switch large scale integrations (LSIs) and has a total I/O throughput of up to 160 Gb/s. A prototype module with total I/O throughput of 100 Gb/s has been partially assembled using eight optical I/O interface blocks, each composed of a 40-ch O/E converter and a 40-ch E/O converter; the data rate per channel is from dc to 700 Mb/s. Using this module we developed an optical I/O interface ATM switch system and confirmed the operation of the optical interface.

OPTIMA: 640 Gb/s high-speed ATM switching system based on 0.25 /spl mu/m CMOS, MCM-C, and optical WDM interconnection

A 640 Gb/s high-speed ATM switching system that is based on the technologies of advanced MCM-C, 0.25 /spl mu/m CMOS and optical WDM interconnection is fabricated for future B-ISDN services. A 40-layer, 160 mm/spl times/114 mm ceramic MCM realizes the basic ATM switch module with 80 Gb/s throughput. The basic unit ATM switch MCM-C consists of an 8-chip advanced 0.25 /spl mu/m CMOS VLSI and 32 chip I/O bipolar VLSIs. The MCM employs a 40 layer, very-thin-layer ceramic MCM and a uniquely structured closed loop type liquid cooling system is adopted to cope with the MCMs high-power dissipation of 230 W. The MCM is mounted on a 32 cm/spl times/50 cm mother board. A three-stage ATM switch is realized by optical WDM interconnection between the high-performance MCMs. For WDM interconnection, newly developed compact size 10 Gb/s, 8 WDM optical transmitters and receivers are used. An optical WDM router based on an AWG (Arrayed WaveGuide) router is used for mesh interconnection of boards. The optical WDM interconnect has 640 Gb/s throughput and easy, simple interconnection. The system, MCM, and optical WDM interconnection will be applied to future B-ISDN backbone networks.

5-Tbit/s frame-based ATM switching system using 2.5-Gbit/s/spl times/8 optical WDM links

The hardware architecture of a 5-Tbit/s FB (frame-based) ATM switching system OPTIMA-2 (OPTically Interconnected Distributed Multi-stage Tbit/s-ATM switching Network Architecture-2) is described. OPTIMA-2 has a non-blocking 3-stage switch architecture employing optical WDM links and dynamic bandwidth sharing. The WDM links are composed of a sender port, wavelength arrayed waveguided grating (AWG) router and receiver port. The sender port at the output port of a switch-element allocates a packet to one of eight WDM wavelengths and transmits it. The receiver port receives packets of all eight wavelengths via the wavelength AWG router and merges them at an input port of the next-stage switch-element. Total bandwidth is limited to 10 Gbit/s, but the maximum bandwidth of each wavelength is designed to be 2.5 Gbit/s to prevent the statistical multiplexing gain from falling. A scheduler, which selects variable-length packets from the eight wavelengths, can keep fairness and a small delay. The bandwidth of each wavelength is changed dynamically by the system so that the traffic in each wavelength is equally distributed among the total bandwidth. In OPTIMA-2, variable-length FB-ATM cell, which is familiar with the IP packet, can be switched while keeping the throughput fairness.

Very compact scalable 80 Gbit/s ATM switching module

あらまし スケーラブル超小型 80Gbit/s ATMスイッチングモジュールを開発した.本モジュールには,ス イッチサイズに制限されることなく,拡張性を有する競合制御方式である SDAを採用している.SDAでは,隣 接するスイッチ LSI間を中継する中継バッファを有し,中継バッファと出力バッファの間で競合制御を行うため, 競合制御信号の送受信を隣接する LSI間のみで行えばよい.そのため,スイッチサイズを大きくすると競合制御 時間が大きくなるという従来の競合制御の問題を解決している.また,0.25 μm CMOS/SIMOX(Separation by IMplanted OXygen)技術を採用し,1.25Gbit/sの超高速 I/Oピン速度を用いて LSIのピンネックを緩和 し,10Gbit/s回線を 4× 2 でスイッチングするスイッチ LSIを 7Wで達成した.更に,複数のスイッチ LSIを マルチチップモジュール上にベアチップ実装し,80Gbit/sのスループットを有する超小型スイッチングモジュー ルを実現した. キーワ ドー ATM,スイッチ,競合制御,拡張性,マルチチップモジュール