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Featured researches published by Ryuta Nara.


asia and south pacific design automation conference | 2010

Scan-based attack against elliptic curve cryptosystems

Ryuta Nara; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

Scan-based attacks are techniques to decipher a secret key using scanned data obtained from a cryptography circuit. Public-key cryptography, such as RSA and elliptic curve cryptosystem (ECC), is extensively used but conventional scan-based attacks cannot be applied to it, because it has a complicated algorithm as well as a complicated architecture. This paper proposes a scan-based attack which enables us to decipher a secret key in ECC. The proposed method is based on detecting intermediate values calculated in ECC. By monitoring the 1-bit sequence in the scan path, we can find out the register position specific to the intermediate value in it and we can know whether this intermediate value is calculated or not in the target ECC circuit. By using several intermediate values, we can decipher a secret key. The experimental results demonstrate that a secret key in a practical ECC circuit can be deciphered using 29 points over the elliptic curve E within 40 seconds.


international symposium on circuits and systems | 2010

State-dependent changeable scan architecture against scan-based side channel attacks

Ryuta Nara; Hiroshi Atobe; Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

Scan test is a powerful and popular test technique because it can control and observe the internal states of the circuit under test. However, scan path would be used to discover the internals of crypto hardware, which presents a significant security risk of information leakage. An interesting design-for-test technique by inserting inverters into the internal scan path to complicate the scan structure has been recently presented. Unfortunately, it still carries the potential of being attacked through statistical analysis of the information scanned out from chips. Therefore, in this paper we propose secure scan architecture, called dynamic variable secure scan, against scan-based side channel attack. The modified scan flip-flops are state-dependent, which could cause the output of each State-dependent Scan FF to be inverted or not so as to make it more difficult to discover the internal scan architecture.


Ipsj Transactions on System Lsi Design Methodology | 2011

Scan vulnerability in elliptic curve cryptosystems

Ryuta Nara; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

A scan-path test is one of the most important testing techniques, but it can be used as a side-channel attack against a cryptography circuit. Scan-based attacks are techniques to decipher a secret key using scanned data obtained from a cryptography circuit. Public-key cryptography, such as RSA and elliptic curve cryptosystem (ECC), is extensively used but conventional scan-based attacks cannot be applied to it, because it has a complicated algorithm as well as a complicated architecture. This paper proposes a scan-based attack which enables us to decipher a secret key in ECC. The proposed method is based on detecting intermediate values calculated in ECC. We focus on a 1-bit sequence which is specific to some intermediate values. By monitoring the 1-bit sequence in the scan path, we can find out the register position specific to the intermediate value in it and we can know whether this intermediate value is calculated or not in the target ECC circuit. By using several intermediate values, we can decipher a secret key. The experimental results demonstrate that a secret key in a practical ECC circuit can be deciphered using 29 points over the elliptic curve E within 40 seconds.


Archive | 2012

Scan-Based Side-Channel Attack on the RSA Cryptosystem

Ryuta Nara; Masao Yanagisawa; Nozomu Togawa

Individual authentication increases in importance as network technology advances. IC passport, SIM card and ID card used in entering and leaving management systems are dependent on a cryptography circuit for keeping their security. LSI chips used there usually include cryptography circuits and encrypt/decrypt important data such as ID numbers and electronic money information. However, there is a threat that a secret key may be retrieved from the cryptography LSI chip. Recently, side-channel attacks against a cryptosystem LSI has been reported (Boneh et al., 1997; Brier et al., 2004; Kocher, 1996; Kocher el al., 1999; Schramm el al., 2003). For example, scan-based side-channel attacks which retrieve secret keys in a cryptography LSI have attracted attention over the five years. A scan path is one of the most important testing techniques, where registers are connected in serial so that they can be controlled and observed directly from outside the LSI. Test efficiency can be increased significantly. On the other hand, one can have register data easily by using a scan path, which implies that one can retrieve a secret key in a cryptography LSI. This is a scan-based side-channel attack.


asia and south pacific design automation conference | 2008

Scalable unified dual-radix architecture for montgomery multiplication in GF ( P ) and GF (2 n )

Kazuyuki Tanimura; Ryuta Nara; Shunitsu Kohara; Kazunori Shimizu; Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

Modular multiplication is the most dominant arithmetic operation in elliptic curve cryptography (ECC), which is a type of public-key cryptography. Montgomery multiplication is commonly used as a technique for the modular multiplication and required scalability since the bit length of operands varies depending on the security levels. Also, ECC is performed in GF(P) or GF(2n), and unified architectures for GF(P) and GF(2n) multiplier are needed. However, in previous works, changing frequency or dual-radix architecture is necessary to deal with delay-time difference between GF(P) and GF(2n) circuits of the multiplier because the critical path of GF(P) circuit is longer. This paper proposes a scalable unified dual-radix architecture for Montgomery multiplication in GF(P) and GF(2n). The proposed architecture unifies 4 parallel radix-216 multipliers in GF(P) and a radix-264 multiplier in GF(2n) into a single unit. Applying lower radix to GF(P) multiplier shortens its critical path and makes it possible to compute the operands in the two fields using the same multiplier at the same frequency so that clock dividers to deal with the delay-time difference are not required. Moreover, parallel architecture in GF(P) reduces the clock cycles increased by dual-radix approach. Consequently, the proposed architecture achieves to compute GF(P) 256-bit Montgomery multiplication in 0.23 mus.


IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 2010

Scan-based side-channel attack against RSA cryptosystems using scan signatures

Ryuta Nara; Kei Satoh; Masao Yanagisawa; Tatsuo Ohtsuki; Nozomu Togawa


IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 2009

A scan-based attack based on discriminators for AES cryptosystems

Ryuta Nara; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki


情報処理学会論文誌 論文誌トランザクション | 2011

Scan Vulnerability in Elliptic Curve Cryptosystems (IPSJ Transactions on System LSI Design Methodology Vol.4)

Ryuta Nara; Nozomu Togawa; Masao Yanagisawa


IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 2009

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in

Kazuyuki Tanimura; Ryuta Nara; Shunitsu Kohara; Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki


IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences | 2009

Unified Dual-Radix Architecture for Scalable Montgomery Multiplications in GF ( P ) and GF (2 n )

Kazuyuki Tanimura; Ryuta Nara; Shunitsu Kohara; Youhua Shi; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

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