S. Brandon Keller

Systems and methods for determining activity factors of a circuit design

System and method for determining a highest level signal name in a hierarchical VLSI design

Method and system for analyzing a VLSI circuit design

Computer aided design systems and methods with reduced memory utilization

Method and system for representing hierarchical extracted resistance-capacitance files of a circuit model

Method and system for identifying fets implemented in a predefined logic equation

System and method for determining detail of analysis in a circuit design

System and method for processing configuration information

System and method for iteratively traversing a hierarchical circuit design

System and method for determining wire capacitance for a VLSI circuit