S. C. Song

Dual-metal gate CMOS technology with ultrathin silicon nitride gate dielectric

We report the first demonstration of a dual-metal gate complementary metal oxide semiconductor (CMOS) technology using titanium (Ti) and molybdenum (Mo) as the gate electrodes for the N-metal oxide semiconductor field effect transistors (N-MOSFETs) and P-metal oxide semiconductor field effect transistors (P-MOSFETs), respectively. The gate dielectric stack consists of a silicon oxy-nitride interfacial layer and a silicon nitride (Si/sub 3/N/sub 4/) dielectric layer formed by a rapid-thermal chemical vapor deposition (RTCVD) process. C-V characteristics show negligible gate depletion. Carrier mobilities comparable to that predicted by the universal mobility model for silicon dioxide (SiO/sub 2/) are observed.

Nucleation and growth study of atomic layer deposited HfO2 gate dielectrics resulting in improved scaling and electron mobility

HfO2 films have been grown with two atomic layer deposition (ALD) chemistries: (a) tetrakis(ethylmethylamino)hafnium (TEMAHf)+O3 and (b) HfCl4+H2O. The resulting films were studied as a function of ALD cycle number on Si(100) surfaces prepared with chemical oxide, HF last, and NH3 annealing. TEMAHf+O3 growth is independent of surface preparation, while HfCl4+H2O shows a surface dependence. Rutherford backscattering shows that HfCl4+H2O coverage per cycle is l3% of a monolayer on chemical oxide while TEMAHf+O3 coverage per cycle is 23% of a monolayer independent of surface. Low energy ion scattering, x-ray reflectivity, and x-ray photoelectron spectroscopy were used to understand film continuity, density, and chemical bonding. TEMAHf+O3 ALD shows continuous films, density >9g∕cm3, and bulk Hf–O bonding after 15 cycles [physical thickness (Tphys)=1.2±0.2nm] even on H-terminated Si(100). Conversely, on H-terminated Si(100), HfCl4+H2O requires 50 cycles (Tphys∼3nm) for continuous films and bulk Hf–O bonding. ...

Intrinsic characteristics of high-k devices and implications of fast transient charging effects (FTCE)

Fast transient charging effects (FTCE) are found to be the source of various undesirable characteristics of high-k devices, such as V/sub th/ instability, low DC mobility and poor reliability. The intrinsic characteristics of high-k transistors free from FTCE are demonstrated using ultra-short pulsed I-V measurements, and it is found that the intrinsic mobility of high-k devices can be much higher than what has been observed in DC based measurements. The FTCE model suggests that many of DC characterization methods developed for SiO/sub 2/ devices are not sufficiently adequate for high-k devices that exhibit significant transient charging. The existence of very strong concurrent transient charging during various reliability tests also degrades the validity of test results. Finally, the implication of FTCE on the high-k implementation strategy is discussed.

Dual-metal gate technology for deep-submicron CMOS transistors

Dual-metal gate CMOS devices with rapid-thermal chemical vapor deposited (RTCVD) Si/sub 3/N/sub 4/ gate dielectric were fabricated using a self-aligned process. The gate electrodes are Ti and Mo for the N- and P-MOSFET respectively. Carrier mobilities are comparable to that predicted by the universal mobility model for SiO/sub 2/. C-V characteristics show good agreement with a simulation that takes quantum-mechanical effects into account, and clearly display the advantage of metal over poly-Si gates.

Identification of sub-band-gap absorption features at the HfO2∕Si(100) interface via spectroscopic ellipsometry

Spectroscopic ellipsometry is used to characterize charge trapping defect states in thin HfO2 gate dielectric films deposited by atomic layer deposition on chemically oxidized p-type Si (100) substrates. The intensity of specific absorption features detected below the band gap of HfO2 at 2.9 and 4.75eV is clearly distinguished from the Si critical points; however, repeating this spectroscopic evaluation for identical HfO2 films deposited and annealed on fused silica substrates results in no defect features detected. The HfO2∕Si(100) results, therefore, suggest these oxygen deficient defects are not intrinsic to HfO2 but reside primarily at the interface with the silicon substrate. The feasibility of utilizing spectroscopic ellipsometry to identify stoichiometric variations at the SiO2∕Si(100) interface and the corresponding changes associated with the electrical performance is presented.

A Novel Electrode-Induced Strain Engineering for High Performance SOI FinFET utilizing Si (1hannel for Both N and PMOSFETs

If Si (110) channel can be used for both nMOS and pMOS FinFET, the implementation of FinFET can be simplified significantly. Electron mobility degradation at Si(110) channel of finFET has been one of the major barriers in this path. We report a creative method to improve electron and hole mobilities using a novel metal electrode induced-strain engineering, which also features the effective workfunction tuning of single metal electrode on high-k dielectric. Compared to planar SOI devices, our optimized SOI FinFETs with metal/high-k stack showed high field mobility for a (110)/lang110rang nMOSFETs, which increased almost two times. By optimizing the workfunction and the strain effect, we achieved an Ion of 930 muA/mum and 680muA/mum for nMOSFETs and pMOSFETs without implementing any other stress engineering process

Highly Manufacturable 45nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration

This paper reports the first demonstration of dual high-k and dual metal gate (DHDMG) CMOSFETs meeting the device targets of 45nm low stand-by power (LSTP) node. This novel scheme has several advantages over the previously reported dual metal gate integration, enabling the high-k and metal gate processes to be optimized separately for N and PMOSFETs in order to maximize performance gain and process controllability. The proposed gate stack integration results in a symmetric short channel Vt of ~plusmn0.45V with >80% high field mobility for both N and PMOSFETs and significantly lower gate leakage compared to poly/SiON stack

Integration of dual metal gate CMOS with TaSiN (NMOS) and Ru (PMOS) gate electrodes on HfO/sub 2/ gate dielectric

We report the process module development results and device characteristics of dual metal gate CMOS with TaSiN and Ru gate electrodes on HfO/sub 2/ gate dielectric. The wet etch of TaSiN had a minimal impact on HfO/sub 2/ (/spl Delta/EOT<1/spl Aring/). A plasma etch process has been developed to etch Ru/TaN/Poly (PMOS) and TaSiN/Ru/TaN/Poly (NMOS) gate stacks simultaneously. Well behaved dual metal gate CMOS transistors have been demonstrated with L/sub g/ down to 85nm.

Charge trapping and detrapping characteristics in hafnium silicate gate dielectric using an inversion pulse measurement technique

Threshold voltage (VTH) instability in metal oxide semiconductor field transistors (MOSFETs) with high dielectric constant (k) gate dielectrics has been investigated with an inversion pulse measurement technique, which can detect fast dielectric charging/discharging within microseconds (μs). The results indicate that VTH instability can be significantly underestimated by conventional VTH measurement techniques. Based on temperature-dependent stress data, it is suggested that charging and discharging are determined by direct tunneling and thermally assisted processes, respectively.

Mechanism of V fb roll-off with High Work function Metal Gate and Low Temperature Oxygen Incorporation to Achieve PMOS Band Edge Work function

V_fb roll-off phenomena in high work function (WF) metal gate on high-k is successfully explained by progressive oxygen vacancy (V_o ⁺) generation in high-k as bottom oxide scales. Based on this understanding, low temperature O incorporation (LTOI) process has been developed, which reduces PMOS V_t significantly by enriching high-k with O without increasing equivalent oxide thickness (EOT).