S. Callier

SPIROC (SiPM Integrated Read-Out Chip): dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35 m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100 ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memory content (time and charge on 2 gains). The data are then stored in a 4 kbytes RAM. A very complex digital part has been integrated to manage all theses features and to transfer the data to the DAQ which is described on [2].

Petiroc and Citiroc: front-end ASICs for SiPM read-out and ToF applications

Petiroc and Citiroc are the two latest ASIC from Weeroc dedicated to SiPM read-out.Petiroc is a 16-channel front-end ASIC designed to readout silicon photomultipliers (SiPMs) for particle time-of-flight measurement applications. It combines a very fast and low-jitter trigger with an accurate charge measurement.Citiroc is a 32-channel front-end ASIC designed to readout silicon photo-multipliers (SiPM). It allows triggering down to 1/3 pe and provides the charge measurement with a good noise rejection. Moreover, Citiroc outputs the 32-channel triggers with a high accuracy (100 ps).Each channel of both ASICs combines a trigger path with an accurate charge measurement path. An adjustment of the SiPM high voltage is possible using a channel-by-channel input DAC. That allows a fine SiPM gain and dark noise adjustment at the system level to correct for the non-uniformity of SiPMs.Timing measurement down to 16 ps RMS jitter for Petiroc and 100 ps RMS for Citiroc is possible along with 1% linearity energy measurement up to 2500 pe. The power consumption is around 3.5 mW/channel for Petiroc and 3 mW/channel for Citiroc, excluding ASICs outing buffer.

Silicon Photomultiplier integrated readout chip (SPIROC) for the ILC: Measurements and possible further development

The SPIROC chip is a dedicated very front-end ASIC chip for an ILC hadronic calorimeter technical prototype with Silicon Photomultiplier (or MPPC) readout. This ASIC is due to equip a 2,000-channel demonstrator in 2009. The SPIROC chip is the successor of the ILC SiPM ASIC presently used for the ILC AHCAL physics prototype, incorporating additional features like auto-triggering, pipelines, digitization as well as power pulsing. Realized in 0.35μm SiGe technology, it is designed in order to fulfill ILC final detector requirements of large dynamic range, low noise, low power consumption, high precision and large channel numbers. The SPIROC is a 36-channel chip. Each channel has bi-gain amplification, auto-triggering capability, a 16-bit depth analog memory array and a 12-bit wilkinson ADC. It allows time and charge measurements at the same time with digitized data results. The digitization is controlled and read out by the digital part of the chip. After the submission in June 2007, extensive measurements have been carried out to characterize the chip. This chip has been proven to be successful in calorimeter calibration as well as real physics experiments. Besides of the affirming measurement results, possible improvements are proposed in order to make the chip even more versatile in dealing with a large variety of Silicon Photomultipliers.

The MU-RAY project: detector technology and first data from Mt. Vesuvius

Muon Radiography allows to map the density of a volcanic cone. It is based on the measurement of the attenuation of the flux of muons present in the cosmic radiation on the ground. The MU-RAY project has developed an innovative detector designed for the muon radiography. The main features are the low electric power consumption, robustness and transportability, good spatial resolution and muon time of flight measurement. A 1 m2 detector prototype has been constructed. and collected data at Mt. Vesuvius for approximately 1 month in spring 2013. A second campaign of measurement has been performed at the Puy de Dome, France, in the last four months of 2013. In this article the principles of muon radiography, the MU-RAY detector and the first results from the collected data will be described.

Triroc: A Multi-Channel SiPM Read-Out ASIC for PET/PET-ToF Application

Triroc is the latest addition to SiPM readout ASICs family developed at Weeroc, a start-up company from the Omega microelectronics group of IN2P3/CNRS. This chip is developed under the framework TRIMAGE European project which is aimed for building a cost effective tri-modal PET/MR/EEG brain scan. To ensure the flexibility and compatibility with any SiPM in the market, the ASIC is designed to be capable of accepting negative and positive polarity input signals. This 64-channel ASIC, is suitable for SiPM readout which requires high accuracy timing and charge measurements. Targeted applications would be PET prototyping with time-of-flight capability. Main features of Triroc includes high dynamic range ADC up to 2500 photoelectrons and TDC fine time binning of 40 ps. Triroc requires very minimal external components which means it is a good contender for compact multichannel PET prototyping. Triroc is designed by using AMS 0.35 μm SiGe technology and it was submitted in March 2014. The detail design of this chip will be presented.

SPIROC: design and performances of a dedicated very front-end electronics for an ILC Analog Hadronic CALorimeter (AHCAL) prototype with SiPM read-out

For the future e+ e- International Linear Collider (ILC) the ASIC SPIROC (Silicon Photomultiplier Integrated Read-Out Chip) was designed to read out the Analog Hadronic Calorimeter (AHCAL) equipped with Silicon Photomultiplier (SiPM). It is an evolution of the FLC_SiPM chip designed by the OMEGA group in 2005. SPIROC2 [1] was realized in AMS SiGe 0.35 μm technology [2] and developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of read-out channels. This ASIC is a very front-end read-out chip that integrates 36 self triggered channels with variable gain to achieve charge and time measurements. The charge measurement must be performed from 1 up to 2000 photo-electrons (p.e.) corresponding to 160 fC up to 320 pC for SiPM gain 106. The time measurement is performed with a coarse 12-bit counter related to the bunch crossing clock (up to 5 MHz) and a fine time ramp based on this clock (down to 200 ns) to achieve a resolution of 1 ns. An analog memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. The analog memory content (time and charge) is digitized thanks to an internal 12-bit Wilkinson ADC. The data is then stored in a 4kbytes RAM. A complex digital part is necessary to manage all these features and to transfer the data to the DAQ. SPIROC2 is the second generation of the SPIROC ASIC family designed in 2008 by the OMEGA group. A very similar version (SPIROC2c) was submitted in February 2012 to improve the noise performance and also to integrate a new TDC (Time to Digital Converter) structure. This paper describes SPIROC2 and SPIROC2c ASICs and illustrates the main characteristics thank to a series of measurements.

HARDROC1, readout chip of the Digital HAdronic CALorimeter of ILC

HARDROC (HAdronic Rpc Detector ReadOut Chip) is the very front end chip designed for the readout of the RPC or Micromegas foreseen for the Digital HAdronic CALorimeter (DHCAL) of the future International Linear Collider. The very fine granularity of the ILC hadronic calorimeters (1cm2 pads) implies a huge number of electronics channels (4 105 /m3) which is a new feature of “imaging” calorimetry. Moreover, for compactness, the chips must be embedded inside the detector making crucial the reduction of the power consumption to 10 µWatt per channel. This is achieved using power pulsing, made possible by the ILC bunch pattern (1 ms of acquisition data for 199 ms of dead time). HARDROC readout is a semi-digital readout with two or three thresholds (2 or 3 bits readout respectively in hardroc1 and hardroc2) which allows both good tracking and coarse energy measurement, and also integrates on chip data storage. The 64 channels of the 2nd prototype, HARDROC2, are made of: • Fast low impedance preamplifier with a variable gain over 8 bits per channel • A variable slow shaper (50-150ns) and Track and Hold to provide a multiplexed analog charge output up to 15pC. • 3 variable gain fast shapers followed by 3 low offset discriminators to autotrig down to 10 fC up to 10pC. The thresholds are loaded by 3 internal 10 bit- DACs and the 3 discri outputs are sent to a 3 inputs to 2 outputs encoder • A 128 deep digital memory to store the 2*64 encoded outputs of the 3 discriminators and bunch crossing identification coded over 24 bits counter. • Power pulsing and integration of a POD (Power On Digital) module for the 5MHz and 40 Mhz clocks management during the readout, to reach 10µW/channel The overall performance of HARDROC will be described with detailed measurements of all the characteristics. Hundreds of chips have indeed been produced and tested before being mounted on printed boards developed for the readout of large scale (1m2) RPC and Micromegas prototypes. These prototypes have been tested with cosmics and also in testbeam at CERN in 2008 and 2009 to evaluate the performance of different kinds of GRPCs and to validate the semi-digital electronics readout system in beam conditions.

SKIROC2_CMS an ASIC for testing CMS HGCAL

SKIROC2_CMS is a chip derived from CALICE SKIROC2 that provides 64 channels of low noise charge preamplifiers optimized for 50 pF pin diodes and 10 pC dynamic range. They are followed by high gain and low gain 25 ns shapers, a 13-deep 40 MHz analog memory used as a waveform sampler at 40 MHz. and 12-bit ADCs. A fast shaper followed by discriminator and TDC provide timing information to an accuracy of 50 ps, in order to test TOT and TOA techniques at system level and in test-beam. The chip was sent to fabrication in January 2016 in AMS SiGe 0,35 μm and was received in May. It was tested in the lab during the summer and will be mounted on sensors for beam-tests in the fall.

SiPM based photon counting detector for scanning digital radiography

In the present report, we summarize the results of our efforts to create a x-ray counting detector for digital scanning radiography based on the silicon photomultipliers (SiPM) at Budker Institute of Nuclear Physics for the last year. We have performed a comparative study of the possible candidates for scintillator—YAP, LFS-3, LGSO, LYSO and two types of SiPMs—HAMAMATSU MPPC with 25 μ m pixel (S10362-33-025C) and KETEK SiPM with 15 μ m pixel (MP15V9 type) o 2.5 mm. To measure real detector parameters we have built a detector prototype based on a 32-channel Omega EASIROC front-end chip. The results obtained in this study demonstrate that such detector could reach quantum efficiency >95%, counting rate —5 MHz, energy resolution ~ 34% (at 59.5 keV) and spatial resolution that is determined by scintillator and SiPM size.

SiW ECAL for future

Calorimeters with silicon detectors have many unique features and are proposed for several world-leading experiments. We discuss the tests of the first three 18×18 cm2 layers segmented into 1024 pixels of the technological prototype of the silicon-tungsten electromagnetic calorimeter for a future e+e− collider. The tests have beem performed in November 2015 at CERN SPS beam line.