S. Celma

Variable frequency sinusoidal oscillators based on CCII/sup +/

Using the two-integrator loop biquadratic general structure and positive second-generation current conveyor (CCII/sup +/) as the active elements, a set of variable frequency sinusoidal oscillators is synthesized. Some of the derived structures are new and three of them have been carefully analyzed because of their special interest at high frequency. Experimental results show an excellent agreement with theoretical predictions. Finally, it is shown that an extensive relation of oscillating configurations reported in the literature could be derived from the general block diagram proposed in this paper.

Current feedback amplifier based sinusoidal oscillators

This paper illustrates the use of a new class of amplifiers known as current feedback amplifiers as the active devices in sinusoidal oscillators. From theoretical analysis, supported by experiments, it is concluded that they offer improved performance regarding their opamp-based counterparts in terms of frequency accuracy, dynamic range, distortion level, and frequency span. At the same time they seem to be more flexible for the inclusion of automatic gain control schemes. >

Low-Voltage Linearly Tunable CMOS Transconductor With Common-Mode Feedforward

This paper presents a new low-voltage pseudodifferential continuous-time CMOS transconductor for wide-band applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Measurements results for a 0.35-m CMOS design show a 1:2 tuning range with total harmonic distortion figures at 10 MHz below 58 dB over the whole range up to a 200- differential output current. The proposed cell consumes less than 1.1 mW from a single 1.8-V supply.

An Ultralow-Power Low-Voltage Class-AB Fully Differential OpAmp for Long-Life Autonomous Portable Equipment

This brief presents an ultralow-power class-AB operational amplifier (OpAmp) designed in a low-cost 0.18- μm CMOS technology. The proposed circuit uses transistors biased in the subthreshold region for low-voltage low-power operation. For a 0.8-V single supply, this OpAmp has 51-dB open-loop gain, 57-kHz unity-gain frequency, 60° phase margin, and 65-dB common-mode rejection ratio for 8-pF loads with a power consumption of only 1.2 μW. Experimental results illustrate performances such as a 0.14-V/μs slew rate and a 750-mV linear output swing, demonstrating its correct functionality.

Wien-type oscillators using CCII+

The purpose of this paper is to show that exists a close relationship between some CCII+ based sinusoidal oscillators and the RC active second order oscillators with a single VCVS. These structures with CCII+ may be derived from the classic Wien-bridge oscillator, and four of them exhibit practical interest. They are canonical, the oscillation condition can be adjusted by a single resistor, and furthermore, they may be designed with the same procedure as their voltage amplifier counterparts. Experimental and simulation results supporting the theoretical analysis are given.

A High-Performance CMOS Feedforward AGC Circuit for a WLAN Receiver

This paper presents a fast-settling compact feedforward automatic-gain-control (AGC) circuit suitable for use in wireless local-area network receivers with orthogonal frequency-division multiplexing (OFDM). The use of these signals introduces stringent settling-time constraints which limit the use of traditional closed-loop feedback amplifiers. Furthermore, the amplitude detection of OFDM signals cannot be performed by a typical peak detector (PD) due to their high peak-to-average power ratio; as a consequence, a novel fast-settling PD is employed to solve this task. The AGC has been implemented in a low-cost 0.35-μm CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 2.4 mW at frequencies as high as 100 MHz, while its gain ranges from 0 to 22 dB in 2-dB steps through a 5-b word. The settling time of the circuit is below 2.4 μs (three symbols).

A transformation method for equivalent infinite-gain op amp to unity-gain CCII networks

A method to obtain equivalent networks is proposed. This permits one to synthesize filters with unity-gain CCII/sup /spl plusmn// from well-known single infinite-gain op amp configurations. Current transmittance filters with high output impedance and voltage transmittance filters with high input impedance are obtained. These circuits have the same passive sensitivities as their op amp counterparts. So, many particular cases proposed in the literature can be understood from a unified viewpoint.

SiGe Analog AGC Circuit for an 802.11a WLAN Direct Conversion Receiver

This brief presents a baseband automatic gain control (AGC) circuit for an IEEE 802.11a wireless local area network (WLAN) direct conversion receiver. The whole receiver is to be fully integrated in a low-cost 0.25- mum 75-GHz SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) process; thus, the AGC has been implemented in this technology by employing newly designed cells, such as a linear variable gain amplifier (VGA) and a fast-settling peak detector. Due to the stringent settling-time constraints of this system, a feedforward gain control architecture is proposed to achieve fast convergence. The proposed AGC is composed of two coarse-gain stages and a fine-gain stage, with a feedforward control loop for each stage. It converges with a gain error of below plusmn1 dB in less than 3.2 mus, whereas the power and area consumption are 13.75 mW and 0.225 mm2 , respectively.

Design of a Novel Envelope Detector for Fast-Settling Circuits

A novel envelope detector structure that overcomes the traditional tradeoff required in these circuits, improving both the tracking and keeping of the signal, which is specially advantageous for fast-settling circuits, is proposed in this paper. The method relies on holding the signal by two capacitors in parallel, discharging one when the other is in the hold mode and employing the held signals to form the output. Results show a savings greater than 60% of the capacitor area for the same ripple ( < 1%) and a release time constant that is 13 times smaller than that obtained by conventional circuits.

12-b Enhanced Input Range On-Chip Quasi-Digital Converter With Temperature Compensation

This brief presents a monolithic 1.8-V 0.18-μm CMOS temperature-compensated voltage-to-frequency converter for sensor read-out interfaces in wireless sensor network applications. Measurement results show that the proposed converter features are suitable for an output frequency span of 2 MHz with an input voltage range of 0.1-1.6 V. This converter presents a relative error below 4.8% and a linearity error below 0.017% (i.e., 12 b) over the whole frequency span for a range of ( -40°C, + 85°C). Power consumption is 0.423 mW (20 nW in sleep mode), and it occupies an active area of 137 μm x 100 μm.