S. Graffi

Failures induced on analog integrated circuits by conveyed electromagnetic interferences: A review

Abstract Failures induced on analog integrated circuits by electromagnetic interference (EMI) will be analyzed with particular emphasis on integrated operational amplifiers built with different technologies. Additionally, the correlation found between EMI susceptibility and large-signal opamp behavior will be discussed. Some criteria for the design of low EMI susceptibility opamps will be derived. Finally, as an application example, the design of a BiCMOS opamp with an extremely low-probability EMI-induced failure will be presented.

New macromodels and measurements for the analysis of EMI effects in 741 op-amp circuits

Presents the design of two macromodels for the 741 op-amp that prove trustworthy in simulating the consequences of high-frequency, large-amplitude sinusoidal voltages that represent EMI (electromagnetic interference) effects and are applied to the input of inverting and noninverting amplifiers. One of the macromodels accounts for power supply voltage change, reproduces correct voltage waveforms at the main nodes of the full circuit, and gives rise to computer time saving factors of 5 or more in comparison with full device-level simulations. The other comprises the minimum number of components necessary to estimate the DC output voltage only and reduces the simulation time by a further factor of about 5. Extensive experimental results were obtained from laboratory measurements and are compared with the numerical simulations. >

CMOS implementation of an analogically programmable cellular neural network

The criteria for designing the basic building blocks of an analogically programmable cellular neural network (CNN) in a 1.5- mu m CMOS technology are reported. The simulated electrical performances of a 10*10 CMOS CNN, consisting of about 8000 MOS transistors, are presented and discussed. It is shown that the designed CNN can be successfully used to perform such useful functions as noise removal, edge detection, hole filling, shadow detection, and connected component recognition. >

Criteria to reduce failures induced from conveyed electromagnetic interferences on CMOS operational amplifiers

Abstract Electromagnetic interference may cause failures in operational amplifiers. The probability of these failures can be reduced by properly designing the opamps, once the failure mechanism has been discovered. In this paper the design of several integrated CMOS operational amplifiers with a very low-probability of electromagnetic interference (EMI) induced failures is reported. In particular, it is shown that opamps exhibiting low EMI-susceptibility can be obtained only if the influence of some parasitic capacitances in the input stage is compensated and if the opamp response to a large square-wave input signal is made symmetric. Following these guide-lines, we designed the two-stage, the folded cascode and the high-swing folded cascode CMOS opamp structures with an EMI susceptibility of only a few tens of mV up to several hundred MHz when driven with interfering input signals of several volts. Additionally, the effect of process parameters variations on EMI induced failures is discussed.

EMI-induced failures in integrated circuit operational amplifiers

Abstract A correlation between failures caused by electromagnetic interference (EMI) and the step response of all-bipolar and FET-input operational amplifiers is discussed. Additionally guidelines for the design of low EMI-susceptibility integrated-circuit opamps are presented. Finally, as an application example, the design and performance of a simple low-probability electromagnetic interference induced failures integrated BiCMOS opamp are reported.

New circuit modeling of operational amplifiers

A description is given of the design of two macromodels for the 741 operational amplifier to be used for computer code simulation of electromagnetic interference (EMI) effects. These macromodels are designed with the ability to work outside the nominal frequency bandwidth of the real circuit in order to simulate the consequences of small and large amplitude signals representing EMI effects. The design starts with the analysis (via numerical simulations) of the full device level model. After the macromodel has been defined, its behavior is adjusted by comparison to experimental measurements on different circuit configurations and interference sources. Measured and simulated results are in agreement.<<ETX>>

Design of integrated BiCMOS operational amplifiers with low-probability EMI-induced-failures

Abstract Electromagnetic interference may cause failures in operational amplifiers. The probability of these failures can be reduced by properly designing the opamp, once the failure mechanism has been discovered. In this paper the design of some integrated BiCMOS operational amplifiers with a very low-probability of electromagnetic interference (EMI) induced failures is reported. In particular, it is shown that opamps exhibiting good general performances as well as low EMI-susceptibility can be obtained only if their response to a large square-wave input signal is symmetric and the influence of some parasitic capacitances in the input stage is compensated. Following these guide-lines, we found possible to design BiCMOS opamp structures exhibiting EMI susceptibility of only a few mV up to several hundred MHz when they are driven with an interfering input signal of some volts.

Circuit macromodels and large‐signal behaviour of fet‐input operational amplifiers

The origin of the slew rate asymmetry found experimentally in FET-input LF355 op amps is analysed in order to explain why macromodels based on a strict build-up technique can fail when used to simulate the behaviour of amplifiers driven by out-of-band large voltage signals. These simulations may be very important in predicting the effects of electromagnetic interferences conveyed to the circuit input port. Other performances of op amp macromodels designed either by build-up techniques or by simplification/build-up techniques are also compared and discussed.

A Unified Approach for Modeling Multiterminal Bipolar and MOS Devices in Smart-Power Technologies

In this work we introduce compact models for both MOS and bipolar transistors used in an advanced smart power technology Deriving the topology of the model on the basis of physical structure and layout geometries we guarantee both physical meaning to model parameters an easy parameters extraction procedure and a similar model structure for parasitic components The models correctly pre dict in uence of parasitic couplings between each component and the collector of the power device showing good agreement with experi mental data

Network Analysis Using Linearization

The sections in this article are 1 A Simple Approach to Linearization 2 A More General Approach to Linearization