S. Iwaida

Level-1 silicon vertex detector trigger at Belle

We present a newly developed fast trigger system that uses the silicon vertex detector (SVD) for the Belle experiment at the KEKB energy-asymmetric e/sup +/e/sup -/ collider. It is designed to issue the trigger with a latency of 1.85 /spl mu/s for the Belle central trigger system (GDL). The primary purpose of the SVD trigger is to reduce beam-induced background events by requiring tracks that come from the interaction point. The system receives trigger signals from VA1TA front-end integrated circuits, which read out signals on the silicon-strips. SVD tracks are constructed with them in combination with the trigger information of the central drift chamber (CDC), which is located outside the SVD. Performance of the SVD trigger is evaluated with collision data.

The Belle L1.5 trigger

During the summer shutdown of 2003 the new silicon vertex detector SVD2 was installed in Belle at the KEK-B factory in Tsukuba, Japan and started to take data in October 2003. It provides important improvements in the tracking capabilities and adds new trigger functionality. In addition a new hardware trigger level 1.5 was designed and installed that takes advantage of the digitized SVD hit data. The improvement in the Belle trigger system is important to deal with the increasing luminosity and higher beam currents of the KEK-B collider. The design of the level 1.5 trigger system is reviewed and results from the data taking are presented.