S. Kanda

Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process

Novel channel-stress enhancement technology on damascene gate process with eSiGe S/D for pFET is demonstrated. It is found for the first time that the damascene gate process featured by the dummy gate removal is more effective in increasing channel strain than the gate-1st process as an embedded SiGe stressor technique is used. Furthermore, an additional channel recess related to the damascene process is shown to enhance channel strain, resulting in a 14% Ion improvement at Ioff = 100 nA/um. We propose combining these strain techniques with high-k/metal gate stacks for low-power and high-performance pFETs.

High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates

CMOS technologies using metal/high-k damascene gate stacks with uniaxial strained silicon channels were developed. Gate electrodes of HfSix and TiN were applied to nFETs and pFETs, respectively. TiN/HfO2 damascene gate stacks and epitaxial SiGe source/drains were successfully integrated for the first time. As a result, drive currents of 1050 and 710 muA/mum at Vdd=l V, Ioff=100 nA/um and Tinv=1.6 nm were obtained for the nFETs and pFETs. The further integration of pFETs on (110) substrates contributed to a higher drive current of 830 muA/mum. These performances were realized under low gate leakage currents of 0.03 A/cm2 and below

Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates

Extreme high-performance n- and pFETs are achieved as 1300 and 1000 uA/um at Ioff = 100 nA/um and Vdd = 1.0 V, respectively, by applying newly proposed booster technologies. The combination of top-cut dual-stress liners and damascene gate remarkably enhances channel stress especially for shorter gate lengths. High-Ion pFETs with compressive stress liners and embedded SiGe source/drain are performed by using ALD-TiN/HfO2 damascene gate stacks with Tinv = 1.4 nm on (100) substrates. On the other hand, nFETs with tensile stress liners are obtained by using HfSix/HfO2 damascene gate stacks with Tinv =1.4 nm.

Ultra High-speed Novel Bulk Thyristor-SRAM (BT-RAM) Cell with Selective Epitaxy Anode (SEA)

We developed novel SRAM cells using bulk thyristor-RAM (BT-RAM). BT-RAM, formed on bulk Si wafers, is low cost and has good compatibility with logic process flows. BT-RAM has excellent performance, with a 100-ps read/write, high Ion/Ioff current ratio (> 108), and low standby current (< 0.5 nA/cell). We can expect the ideal cell size to be as low as 30 F2, one-fourth that of a conventional 6T-SRAM cell, by using selective epitaxy technique for anode regions (SEA). BT-RAM provides us with solutions to many inherent problems in 6T-SRAM in the 65-nm generation and beyond

35-nm gate-length and ultra low-voltage (0.45 V) operation Bulk Thyristor-SRAM/DRAM (BT-RAM) cell with Triple selective Epitaxy Layers (TELs)

We have successfully developed an alternative SRAM cell using a bulk thyristor-RAM (BT-RAM), which has a 35-nm gate-length with triple selective epitaxy layers (TELs) for the anode, the n-base, and the cathode. The TEL BT-RAM reads and writes at an ultra low voltage of 0.45 V at 900 ps and reads and writes at a high speed of 100 ps at 0.9 V. It also has excellent scalability, a high Ion/Ioff ratio, and good thermal stability even at 125degC. The TEL BT-RAM is therefore a promising alternative SRAM cell for the 35-nm gate length generation and beyond.

High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology

We have developed a dual metal gate CMOS technology with HfSi_x for nMOS and Ru for pMOS on HfO₂ gate dielectric. These gate stacks show high mobility (100% of universal mobility for electron, 80% for hole at high fields) down to T_inv of 1.7 nm and symmetrical low V_t equivalent to poly-Si/SiO₂. As a result, high drive currents of 780 muA/mum and 265 muA/mum at I_off = 1 nA/mum are achieved for V_dd = 1.0 V in L_g = 60 nm nMOS and pMOS, respectively We have applied the mobility enhancement technology to the Ru/HfO₂ pMOS by utilizing (110)-substrate. As a result, an excellent drive current of 400 muA/mum (151% improvement over (100)-p⁺poly-Si/SiO₂) is achieved

Low voltage/Sub-ns Operation Bulk Thyristor-SRAM (BT-RAM) Cell with Double Selective Epitaxy Emitters (DEE)

We have successfully developed an alternative SRAM cell for the first time using a Bulk Thyristor-RAM (BT-RAM) with a Double selective Epitaxy technique for two Emitter regions (DEE). The DEE BT-RAM can read/write at Ins at a low-voltage of 0.6 V or read/write at 1.5 V at a high speed of 100 ps. It also has good retention characteristics even at 125degC, suggesting good scalability for gate length of 65 nm and beyond, and its ideal cell size is expected to be 30 F2, one-fourth that of a conventional 6T-SRAM cell. The DEE BT-RAM is therefore a promising alternative SRAM for the 65-nm generation and beyond.

High Performance pMOSFET with ALD-TiN/HfO2 Gate Stack on (110) Substrate by Low Temperature Process

We have developed a high performance pMOSFET with ALD-TiN/HfO2 gate stacks on (110) substrate using gate last process at low temperature. High work function and low gate leakage current are obtained. An extremely high mobility equivalent to P+poly-Si/SiO2 on (110) substrate (171 cm2/Vs at 0.5 MV/cm) is achieved with ALD-TiN/HfO2 on (110) substrate in the thinner Tinv region of 1.7 nm. Vth roll-off characteristics are well controlled down to 50 nm. A high drive current of 380 uA/um at I off = 1 uA/um is achieved at Vdd = 1.0 V. The drive current of ALD-TiN/HfO2 gate stack on (110) substrate is improved 1.4 times compared with (100) substrate and 2.4 times compared with P+poly-Si/SiO2 on (100) substrate

Extremely Low-voltage and High-speed Operation Bulk Thyristor-SRAM/DRAM (BT-RAM) Cell with Triple Selective Epitaxy Layers (TEL)

We have successfully developed an alternative SRAM cell for the first time using a bulk thyristor-RAM (BT-RAM) with triple selective epitaxy layers (TEL) for anode, n-base, and cathode. The n-base of the pnp transistor is a key for the thyristor characteristics. We optimized both the thickness and the dopant concentration of the n-base by using an in-situ doped selective epitaxy technique. We obtained high current gain (beta values) for the pnp transistor in a thyristor, and the TEL BT-RAM cell was thus able to read/write at 200 ps at 0.6 V. It also showed good retention characteristics even at 125degC and the possibility of good scalability for a gate length of 45 nm and beyond. The TEL BT-RAM cell is therefore a promising alternative SRAM and DRAM cell for the future generations.

High performance nMOSFET with HfSi/subx//HfO/sub 2/ gate stack by low temperature process

We propose HfSix/HfO2 gate stacks as the most suitable combination for high performance nMOSFETs. An equivalent work function (WF) to n+poly-Si was obtained by controlling Hf/Si ratio of the electrode. The highest electron mobility ever reported was achieved in the thinner Tinv region down to 1.6 nm by low temperature process without using plasma nitridation both for metal and high-k fabrication. As a result, the extremely high drive current of 1.25mA/mum at off-state leakage of 1 nA/mum and low gate leakage current of 0.3A/cm2 were obtained at Vdd = 1.3V with 65 nm gate length nMOSFETs without strain enhanced technology