S. P. Murarka

Thin film interaction between titanium and polycrystalline silicon

The low resistivity of the titanium disilicide makes this material attractive for gate and interconnect metallizations. TiSi2 has been formed by reacting Ti films with polycrystalline and monocrystalline silicon in the temperature range 400–1100 °C. The interaction is investigated by use of sheet resistance, x‐ray diffraction, and stress measurements. It has been found that Ti and Si react very rapidly to form both TiSi and TiSi2 at temperatures ? 700 °C and only TiSi2 at temperatures ≳ 700 °C. The TiSi2 films are associated with a very low resistivity (∼15 μΩ cm), high tensile stress [∼ (1–2) ×1010 dyn/cm2)], and a rough surface. Silicided structures are mechanically stable. It is proposed that the silicon, as the predominant diffusing species, first diffuses into titanium to completely convert titanium into TiSi and then into TiSi to form TiSi2.

Silicide formation in thin cosputtered (tantalum + silicon) films on polycrystalline silicon and SiO2

Formation of tantalum silicides has been investigated by cosputtering tantalum and silicon on polycrystalline silicon and oxidized silicon wafers. Alloys with as‐deposited Si/Ta atomic ratios of 0.6 to 3 are sintered in hydrogen or argon ambient in the temperature range 400–1000 °C. It is found that for alloys with Si/Ta?1.0 and sintered at temperatures <700 °C, only Ta5Si3 is formed. At higher temperatures and in presence of polycrystalline silicon TaSi2 is formed. In the absence of polycrystalline silicon (i.e., on oxide) only Ta5Si3 is formed at all temperatures. For alloys with Si/Ta ratios ?2 only TaSi2 is formed. In all cases the resistivity decreases as a result of sintering, ending up in a value as a low as ∼50 μΩ cm after 1000 °C/30 min sintering. The stress in the silicided films is found to be nearly 1×1010 dyn/cm2, tensile. The results have been explained on the basis of the fact that in cosputtered films interaction occurs locally which leads to smaller grain size, higher resistivities, lower...

Refractory silicides of titanium and tantalum for low-resistivity gates and interconnects

A study of the refractory-gate metallization schemes had been undertaken to provide a low-resistivity metallization for LSI and VLSI. In this paper, we describe an overview of the efforts made in this direction and present two different metallization schemes which lead to a resistivity of <=20 and 40 /spl mu//spl Omega/spl dot/cm at the gate level. These schemes involve formation of titanium and tantalum silicides on polysilicon gates, respectively. The recommended structure ia a metal or a cosputtered alloy/polysilicon/gate oxide/substrate which, when sintered, gives the desired structure silicide/polysilicon/gate oxide substrate. By the use of 1000-/spl aring/ Ti or Ta, the sheet resistance of nearly 1 or 2 Omega//spl square/, respectively, can be routinely obtained. The silicides are mechanically strong and can be dry etched using radial-flow or barrel-type plasma reactors. The Ta silicide structure is found to be very stable throughout standard processing and can be retrofitted in the present processing sequence. Ti silicide structures are similarly stable except for the reactivity of the silicide with HF-containing reagents. The Ti silicide metallization scheme can therefore be employed in processing with changes incorporated to avoid HF-silicide contact.

Study of cobalt‐disilicide formation from cobalt monosilicide

The reaction CoSi+Si→CoSi2 has been investigated in the temperature range of 500–600 °C, using Rutherford backscattering, x‐ray diffraction, transmission electron microscopy, and four‐point sheet‐resistance measurements. The reaction is very slow at 500 °C and extremely fast at 600 °C, and appears to occur in four stages: (a) nucleation of the CoSi2 phase at the grain‐boundary triple points, (b) lateral growth from nucleation sites to form a continuous layer on the silicon surface, (c) growth in thickness by diffusion through this disilicide layer, and (d) the lateral epitaxial growth by eliminating the grain boundaries. The diffusion through the disilicide layer seems to be a rate‐limiting process with high activation energy.

Effect of phosphorus doping on stress in silicon and polycrystalline silicon

An investigation of the polysilicon stress properties as a function of film thicknesses and phosphorus doping showed that as‐deposited films are moderately compressive, and become less compressive with increasing film thickness. High temperature PBr3 diffusion in silicon produces wafer bending corresponding to a tensile stress in wafer. Following a PBr3 diffusion, polysilicon films, however, become less compressive. Subsequent oxidation introduces an additional compressive stress component of the order of 2−3×109 dyne/cm2 for oxidation temperatures between ∼900−1000 °C. The thermal expansion coefficients were similar for doped and undoped films (α∼2.9 ppm/°C) and slightly less than for 〈100〉 silicon, while the doped films were found to be less stiff than undoped ones but both were less stiff than 〈100〉 silicon. The observed changes in polysilicon stress due to film thickness and phosphorus doping have been interpreted in terms of a grain growth model wherein those factors which lead to enhanced grain grow...

Electrical conduction and breakdown in oxides of polycrystalline silicon and their correlation with interface texture

The electrical properties of oxidized polysilicon (poly‐oxide) were measured for samples of various thicknesses, grown from polysilicon which had been doped at temperatures of 900–1000 °C, and oxidized in steam or dry oxygen at temperatures of 850–1050 °C. The electrical conduction can be explained in terms of Fowler‐Nordheim tunneling at sites of roughness of the polysilicon/poly‐oxide interface, and in terms of deep electron traps near that interface, in agreement with previously published results. We have found additional evidence for such electron traps. We find that higher doping and oxidation temperatures tend to yield oxides with higher breakdown fields, although there is considerable variation among different sets of samples. We observe no significant differences in the polysilicon/poly‐oxide interface texture by cross‐sectional transmission electron microscopy. However, we find a strong correlation between the applied field necessary for a significant leakage current through the poly‐oxide and th...

Oxidation of tantalum disilicide on polycrystalline silicon

Oxidation characteristics of the tantalum disilicide films have been investigated in the temperature range of 900°–1050 °C in dry oxygen and steam ambients. The silicide does not oxidize in dry oxygen and oxidizes in steam at a rate lower than that of doped polycrystalline silicon films as long as there is a polycrystalline silicon layer between the silicide and the gate oxide. Under these circumstances, the silicide retains its electrical and mechanical characteristics. The oxide on the silicide has an etch rate (in buffered hydrofluoric acid) similar to that of thermal SiO2 on silicon. Electrical characteristics of the oxide appear to be similar to those of the wet oxide on polycrystalline silicon. In the absence of polycrystalline silicon, between the silicide and the gate oxide, oxidation leads to a loss in the conductivity of the silicide and eventually to a mechanical instability of the film. An oxidation mechanism, which assumes silicon diffusion by substitution through the silicide, has been proposed.

Oxidation induced stacking faults in n‐ and p‐type (100) silicon

The formation of stacking faults during thermal oxidation of silicon has been investigated. The length and the density of stacking faults, in both n‐ and p‐type 5‐cm‐diam (100) silicon wafers obtained from various manufacturers, were determined as a function of time and temperature of oxidation in dry and steam ambients. There appeared to be two categories of stacking faults. In the first category, the length of the stacking fault was given by L= (const) tn exp(−Q/kT), where n and Q are, respectively, 0.85 and 2.55 eV for dry oxidation and 0.66 and 2.37 eV for steam oxidation. This length was independent of the type (p or n) of the wafer. In the second category, the length of the stacking faults varied randomly across the wafer surface. The number of such faults was only about 5% of the total. For a given oxidation condition, the density of the stacking faults was an order of magnitude or more higher in n‐type wafers than that in p‐type wafers. Except for the very short periods of oxidation (<20 min) the ...

Hexagonal WSi2 in cosputtered (tungsten and silicon) mixture

Hexagonal WSi2 was found to form from nearly amorphous cosputtered (tungsten and silicon) mixtures depostied on oxidized silicon. This form of WSi2 was detected in films sintered at temperatures in the range 400–600 °C. At temperatures of 700 °C or above, only tetragonal WSi2 formed. The hexagonal‐to‐tetragonal transformation temperature was found to be ∼550 °C. At 600 °C the transformation appears to follow a square root of time dependence.

MOS Compatibility of high-conductivity TaSi 2 /n + poly-Si gates

The MOS-VLSI parameters and process compatibility of a high-conductivity refractory silicide gate with a sheet resistance of ∼ 2 Ω/□ have been evaluated. The gate metallization typically consisted of 2.5 kÅ TaSi2/2.5 kÅ poly-Si, which was sintered prior to patterning with a CF4/O2plasma etch. Measurements were made to determine the metal work function, oxide fixed charge, surface-states density, dielectric strength, oxide defect density, lifetime, current leakage, and the flat-band voltage stability with respect to mobile charge contamination, slow trapping, and hot-electron trapping. On IGFETs (500-Å SiO2, As-implanted source/ drain), VTand β measurements were made as a function of the back-gate bias and the channel length as small as 2 µm. The MOS and IGFET parameters are nearly ideal and correspond to those expected of n+poly-Si gates. Static and dynamic bias-temperature aging stability of the VFBis excellent. These characteristics are preserved through subsequent standard VLSI process steps. However, certain process and structure limitations do exist and these have been defined.