S. Q. Zheng

Fast and processor efficient parallel matrix multiplication algorithms on a linear array with a reconfigurable pipelined bus system

We present efficient parallel matrix multiplication algorithms for linear arrays with reconfigurable pipelined bus systems (LARPBS). Such systems are able to support a large volume of parallel communication of various patterns in constant time. An LARPBS can also be reconfigured into many independent subsystems and, thus, is able to support parallel implementations of divide-and-conquer computations like Strassens algorithm. The main contributions of the paper are as follows. We develop five matrix multiplication algorithms with varying degrees of parallelism on the LARPBS computing model; namely, MM/sub 1/, MM/sub 2/, MM/sub 3/, and compound algorithms C/sub 1/(/spl epsiv/)and C/sub 2/(/spl delta/). Algorithm C/sub 1/(/spl epsiv/) has adjustable time complexity in sublinear level. Algorithm C/sub 2/(/spl delta/) implies that it is feasible to achieve sublogarithmic time using /spl sigma/(N/sup 3/) processors for matrix multiplication on a realistic system. Algorithms MM/sub 3/, C/sub 1/(/spl epsiv/), and C/sub 2/(/spl delta/) all have o(/spl Nscr//sup 3/) cost and, hence, are very processor efficient. Algorithms MM/sub 1/, MM/sub 3/, and C/sub 1/(/spl epsiv/) are general-purpose matrix multiplication algorithms, where the array elements are in any ring. Algorithms MM/sub 2/ and C/sub 2/(/spl delta/) are applicable to array elements that are integers of bounded magnitude, or floating-point values of bounded precision and magnitude, or Boolean values. Extension of algorithms MM/sub 2/ and C/sub 2/(/spl delta/) to unbounded integers and reals are also discussed.

Optimal ring embedding in hypercubes with faulty links

The authors show that in an n-dimensional hypercube (Q/sub n/), up to n-2 links can fail before destroying all available Hamiltonian cycles. They present an efficient algorithm which identifies a characterization of a Hamiltonian cycle in Q/sub n/, with as many as n-2 faulty links, in O(n/sup 2/) time. Generating a fault-free Hamiltonian cycle from this characterization can be easily done in linear time. An important application of this work is in optimal simulation of ring-based multiprocessors or multicomputer systems by hypercubes. Compared with the existing fault-tolerant embeddings based on link-disjoint Hamiltonian cycles, the algorithm specifies such a cycle that tolerates twice as many faulty links.<<ETX>>

Finding obstacle-avoiding shortest paths using implicit connection graphs

We introduce a framework for a class of algorithms solving shortest path related problems, such as the one-to-one shortest path problem, the one-to-many shortest paths problem and the minimum spanning tree problem, in the presence of obstacles. For these algorithms, the search space is restricted to a sparse strong connection graph that is implicitly represented and its searched portion is constructed incrementally on-the-fly during search. The time and space requirements of these algorithms essentially depend on actual search behavior. Therefore, additional techniques or heuristics can be incorporated into search procedure to further improve the performance of the algorithms. These algorithms are suitable for large VLSI design applications with many obstacles.

A QoS supporting scheduling algorithm for optical burst switching DWDM networks

The ubiquity of IP has led to IP-over-WDM as the core architecture for the next-generation optical Internet. Optical burst switching (OBS) has been proposed to be a competitive switching technology for DWDM networks. The data channel scheduling algorithm is one of the major challenges in OBS. The same-service-to-all model of the current Internet is inadequate for the diverse quality of service expectations of Internet applications and users. Differentiated service (DiffServ) was proposed to provide a scalable and manageable architecture for service differentiation in IP networks. This paper proposes a scheduling algorithm based on an existing LAUC-VF algorithm to support DiffServ and takes advantage of MPLS. Simulation results demonstrate that this algorithm has better QoS performance than the existing LAUC-VF algorithm.

FAST NEAREST NEIGHBOR ALGORITHMS ON A LINEAR ARRAY WITH A RECONFIGURABLE PIPELINED BUS SYSTEM

Abstract We present efficient algorithms for the nearest neighbor problem defined in an n × n binary image. We show that using a linear array with a reconfigurable pipelined bus system (LARPBS) of n2 processors, the nearest neighbor problem can be solved in O(loglogn) time, and using an LARPBS of n2+∊ processors, for any fixed constant ∊>0. the nearest neighbor problem can be solved in O(l) time. We also show that the nearest neighbor problem can be solved on an LARPBS of n2 processors in O(1) time with high probability.

A general greedy channel routing algorithm

A general approach for the channel routing problem is presented as a framework for a class of heuristic routing algorithms. The algorithm is shown to possess a backtracking capability that increases the chance of completing the routing with a minimum number of tracks. Since the concepts described are general, they can be applied to other channel problems, such as switchbox routing, three-layer routing, and multilayer routing, or even to the overlap model, with only a few modifications. It is shown that track-oriented greedy algorithms can be modified to solve other channel routing problems. As examples, the algorithm is modified to solve the Manhattan switch-box problem and channel routing problems in the overlap and knock-knee models. Preliminary results show that the modified algorithms have good performance and show strong potential to outperform existing algorithms. Applying the algorithm MCRP-ROUT to the benchmark Deutschs difficult problem and Bursteins difficult problem, routing solutions of 19 tracks and six tracks, respectively, were obtained. >

Segmentation and recognition of motion streams by similarity search

Fast and accurate recognition of motion data streams from gesture sensing and motion capture devices has many applications and is the focus of this article. Based on the analysis of the geometric structures revealed by singular value decompositions (SVD) of motion data, a similarity measure is proposed for simultaneously segmenting and recognizing motion streams. A direction identification approach is explored to further differentiate motions with similar data geometric structures. Experiments show that the proposed similarity measure can segment and recognize motion streams of variable lengths with high accuracy, without knowing beforehand the number of motions in a stream.

Efficient Deterministic and Probabilistic Simulations of PRAMs on Linear Arrays with Reconfigurable Pipelined Bus Systems

In this paper, we present deterministic and probabilistic methods for simulating PRAM computations on linear arrays with reconfigurable pipelined bus systems (LARPBS). The following results are established in this paper. (1) Each step of a p-processor PRAM with m=O(p) shared memory cells can be simulated by a p-processors LARPBS in O(log p) time, where the constant in the big-O notation is small. (2) Each step of a p-processor PRAM with m=Ω(p) shared memory cells can be simulated by a p-processors LARPBS in O(log m) time. (3) Each step of a p-processor PRAM can be simulated by a p-processor LARPBS in O(log p) time with probability larger than 1−1/pc for all c>0. (4) As an interesting byproduct, we show that a p-processor LARPBS can sort p items in O(log p) time, with a small constant hidden in the big-O notation. Our results indicate that an LARPBS can simulate a PRAM very efficiently.

Pipelined asynchronous time-division multiplexing optical bus

S. Q. ZhengLouisiana State UniversityDepartment of Computer Science,andDepartment of Electrical and ComputerEngineeringBaton Rouge, Louisiana 70803E-mail: zheng@bit.csc.lsu.eduYueming LiLouisiana State UniversityDepartment of Computer ScienceBaton Rouge, Louisiana 70803Abstract. We propose a pipelined asynchronous time-division multi-plexing optical bus. Such a bus can use one of two hardwared priorityschemes: the linear priority scheme and the round-robin priority scheme.Our simulation results show that the performance of the proposed bus issignificantly better than the performances of known pipelined synchro-nous time-division multiplexing optical buses. The possibilities of usingour buses to construct multichannel switches and multidimensional pro-cessor arrays are also discussed.

Optimal simulation of linear multiprocessor architectures on multiply-twisted cube using generalized Gray Codes

We consider the problem of simulating linear arrays and rings on the multiply twisted cube. We introduce a new concept, the reflected link label sequence, and use it to define a generalized Gray Code (GGC). We show that GGCs can be easily used to identify Hamiltonian paths and cycles in the multiply twisted cube. We also give a method for embedding a ring of arbitrary number of nodes into the multiply twisted cube.