S. Simon Wong

Physical modeling of spiral inductors on silicon

This paper presents a physical model for planar spiral inductors on silicon, which accounts for eddy current effect in the conductor, crossover capacitance between the spiral and center-tap, capacitance between the spiral and substrate, substrate ohmic loss, and substrate capacitance. The model has been confirmed with measured results of inductors having a wide range of layout and process parameters. This scalable inductor model enables the prediction and optimization of inductor performance.

Temperature-Dependent Thermal Conductivity of Single-Crystal Silicon Layers in SOI Substrates

Self heating diminishes the reliability of silicon-on-insulator (SOI) transistors, particularly those that must withstand electrostatic discharge (ESD) pulses. This problem is alleviated by lateral thermal conduction in the silicon device layer, whose thermal conductivity is not known. The present work develops a technique for measuring this property, and provides data for layers in wafers fabricated using bond-and-etch-back (BESOI) technology. The room-temperature thermal conductivity data decrease with decreasing layer thickness, d s , to a value nearly 40 percent less than that of bulk silicon for d s = 0.42 μm, The agreement of the data with the predictions of phonon transport analysis between 20 and 300 K strongly indicates that phonon scattering on layer boundaries is responsible for a large part of the reduction. The reduction is also due in part to concentrations of imperfections larger than those in bulk samples. The data show that the buried oxide in BESOI wafers has a thermal conductivity that is nearly equal to that of bulk fused quartz. The present work will lead to more accurate thermal simulations of SOI transistors and cantilever MEMS structures.

Phonon-boundary scattering in thin silicon layers

Temperature fields in microdevices made from silicon-on-insulator (SOI) wafers are strongly influenced by the lateral thermal conductivity of the silicon overlayer, which is diminished by phonon scattering on the layer boundaries. This study measures the thermal conductivity of single-crystal silicon layers in SOI substrates at temperatures between 20 and 320 K using Joule heating and electrical-resistance thermometry in microfabricated structures. Data for layers of thickness between 0.4 and 1.6 μm demonstrate the large reduction resulting from phonon-boundary scattering, particularly at low temperatures, and are consistent with predictions based on the phonon Boltzmann transport equation.

High-gain lateral bipolar action in a MOSFET structure

A hybrid-mode device based on a standard submicrometer CMOS technology is presented. The device is essentially a MOSFET in which the gate and the well are internally connected to form the base of a lateral bipolar junction transistor (BJT). At low collector current levels, lateral bipolar action with a current gain higher than 1000 is achieved. No additional processing steps are needed to obtain the BJT when the MOSFET is properly designed. n-p-n BJTs with a 0.25- mu m base width have been successfully fabricated in a p-well 0.25- mu m bulk n-MOSFET process. The electrical characteristics of the n-MOSFET and the lateral n-p-n BJT at room and liquid nitrogen temperatures are reported. >

A 10-GHz global clock distribution using coupled standing-wave oscillators

In this paper, a global clock network that incorporates standing waves and coupled oscillators to distribute a high-frequency clock signal with low skew and low jitter is described. The key design issues involved in generating standing waves on a chip are discussed, including minimizing wire loss within an available technology. A standing-wave oscillator, which is a distributed oscillator that sustains ideal standing waves on lossy wires, is introduced. A clock grid architecture comprised of coupled standing-wave oscillators and differential low-swing clock buffers is presented, along with a compact circuit model for networks of oscillators. The measured results for a prototyped standing-wave clock grid operating at 10 GHz and fabricated in a 0.18-/spl mu/m 6M CMOS logic process are presented. A technique is proposed for on-chip skew measurements with subpicosecond precision.

Integrated CMOS transmit-receive switch using LC-tuned substrate bias for 2.4-GHz and 5.2-GHz applications

CMOS transmit-receive (T/R) switches have been integrated in a 0.18-/spl mu/m standard CMOS technology for wireless applications at 2.4 and 5.2 GHz. This switch design achieves low loss and high linearity by increasing the substrate impedance of a MOSFET at the frequency of operation using a properly tuned LC tank. The switch design is asymmetric to accommodate the different linearity and isolation requirements in the transmit and receive modes. In the transmit mode, the switch exhibits 1.5-dB insertion loss, 28-dBm power, 1-dB compression point (P/sub 1dB/), and 30-dB isolation, at 2.4 and 5.2 GHz. In the receive mode, the switch achieves 1.6-dB insertion loss, 11.5-dBm P/sub 1dB/, and 15-dB isolation, at 2.4 and 5.2 GHz. The linearity obtained in the transmit mode is the highest reported to date in a standard CMOS process. The switch passes the 4-kV Human Body Model electrostatic discharge test. These results show that the switch design is suitable for narrow-band applications requiring a moderate-high transmitter power level (<1 W).

Near speed-of-light signaling over on-chip electrical interconnects

The propagation limits of electrical signals for systems built with conventional silicon processing are explored. A design which takes advantage of the inductance-dominated high-frequency regime of on-chip interconnect is shown capable of transmitting data at velocities near the speed of light. In a 0.18-/spl mu/m six-level aluminum CMOS technology, an overall delay of 283 ps for a 20-mm-long line, corresponding to a propagation velocity of one half the speed of light in silicon dioxide, has been demonstrated. This approach offers a five times improvement in delay over a conventional repeater-insertion strategy.

CMOS RF integrated circuits at 5 GHz and beyond

A strong demand for wireless products, an insatiable thirst for spectrum that pushes carrier frequencies ever upward, and the constant quest for higher performance at lower power and cost, have recently driven the development of radio frequency integrated circuit (RFIC) technology in unprecedented ways. These pressures are stimulating novel solutions that allow RFICs to enjoy more of the benefits of Moores law than has been the case in the past. In addition to regular raw transistor speed increases, the growing number of interconnect layers allows the realization of improved inductors, capacitors, and transmission lines. A deeper understanding of noise at both the device and circuit level has improved the performance of low noise amplifiers (LNAs) and oscillators. Finally, an appropriate raiding of circuit ideas dating back to the vacuum tube era enables excellent performance, even when working close to the limits of a technology. This paper surveys some of these developments in the context of low-power RF CMOS technology, with a focus on an illustrative implementation of a low-power 5-GHz wireless LAN receiver in 0.25-/spl mu/m CMOS. Thanks to these recent advances in passive components and active circuits, the blocks comprising the receiver consume a total of approximately 37 mW. These blocks include an image-reject LNA, image-reject downconverter, and a complete frequency synthesizer. The overall noise figure is 5 dB, and the input-referred third-order intercept (IIP3) is -2 dBm. To underscore that 5 GHz does not represent an upper bound by any means, this paper concludes with a look at active circuits that function beyond 15-20 GHz, and a characterization of on-chip transmission lines up to 50 GHz, all in the context of how scaling is expected to shape future developments.

Kinetics of copper drift in low-/spl kappa/ polymer interlevel dielectrics

This paper addresses the drift of copper ions (Cu/sup +/) in various low-permittivity (low-/spl kappa/) polymer dielectrics to identify copper barrier requirements for reliable interconnect integration in future ULSI. Stressing at temperatures of 150-275/spl deg/C and electric fields up to 1.5 MV/cm was conducted on copper-insulator-silicon capacitors to investigate the penetration of Cu/sup +/ into the polymers. The drift properties of Cu/sup +/ in six industrially relevant low-/spl kappa/ organic polymer insulators-parylene-F, benzocyclobutene, fluorinated polyimide, an aromatic hydrocarbon, and two varieties of poly(arylene ether)-were evaluated and compared by capacitance-voltage, current-time, current-voltage, and dielectric time-to-failure measurements. Our study shows that Cu/sup +/ drifts readily into fluorinated polyimide and poly(arylene ether), more slowly into parylene-F, and even more slowly into benzocyclobutene. Among these polymers, the copper drift barrier property appears to be improved by increased polymer crosslinking and degraded by polar functional groups in the polymers. A thin nitride cap layer can stop the drift. A physical model has been developed to explain the kinetics of Cu/sup +/ drift.

Analysis and optimization of accumulation-mode varactor for RF ICs

This paper presents a novel RF IC varactor implemented in a standard CMOS process. This device has shown a remarkable tuning range of 150%, sensitivity of 300%/V, and quality factor of 23 at 1 GHz. A physical model of the varactor is presented and confirmed with measured data. Using the model derived, optimization has shown that a Q as high as 200 can be achieved.