S. Strahle

Dual-gate HFET with closely spaced electrodes on InP

An InGaAs/AlInAs dual-gate HFET with two closely spaced gate electrodes deposited in a common gate recess has been fabricated on InP substrate. The configuration consists of an 0.25 /spl mu/m RF-driven /spl Gamma/-gate overlapping to the source and a DC-trapezoid control gate placed approximately 0.2 /spl mu/m behind the /spl Gamma/-gate. The fabrication sequence allows one to test the device as a single gate FET before deposition of the second gate. The influence of the second gate on the transistor performance was characterized under DC- and RF-conditions. The device current could be fully modulated by either gate and the small signal RF behaviour could be tested in all modes of operation with the second gate RF-grounded. In comparison with the single gate FET, the dual-gate configuration shows an essentially reduced feedback behaviour with reduced C/sub dg/ and G/sub ds/ however, slightly increased input capacitance C/sub gs/. At V/sub ds/=1.2 V f/sub max/ is enhanced by 40%, from 190 GHz to 260 GHz, whereas the gain-bandwidth product decreases from 90 GHz to 70 GHz. The increase of f/sub max/ is strongly drain bias dependent and increases steeply beyond V/sub ds/=1.0 V.

High field drift domains in GaAs and InP based heterostructure field effect devices

Modelling the high field drift region of HFETs as a drift capacitance between gate and drain in series with the gate capacitance allows one to estimate the extension of the drift region, which determines feedback and output conductance, thus relating the microwave power gain to the device structure. The technique is applied to various GaAs and InP based FET structures.<<ETX>>

Drift region characteristics of InP-based HEMT devices evaluated by a simple drift region model

InP-based HEMTs exhibit superior high frequency performance compared to GaAs PS-HEMTs. This is commonly attributed to a higher electron mobility, saturated velocity and better carrier confinement in the GaInAs QW-channel. Whereas the parameters determining f/sub t/ are well documented, the influence of the carrier confinement and electron dynamics on f/sub max/ is less clear. Intrinsically, a high f/sub max/ relies essentially on the efficiency of the gate-drain high field drift region to separate input and output. Thus, the impact of this region on f/sub max/ has been extensively studied analytically and numerically in the past. Due to the complex electron dynamics involved and the 2D-nature of this region, most models are limited to specific structures and only few general design criteria exist. In this study three structures are compared: an AlInAs/GaInAs HEMT structure on InP is analysed in detail and compared with a GaAs PM-HEMT device and a novel InP-based HEMT structure containing a composite GaInAs-InP QW channel. As mentioned above, the high f/sub max/ of InP-based HEMTs is generally attributed to an improved hot electron confinement. The analysis presented here, however, reveals that the high f/sub max/ of the InP-based devices is mainly linked to an extended lateral drift region and not to an improved carrier confinement.<<ETX>>

Two layer stepped-QW channel HFETs on InP-substrate

A novel HFET structure on InP containing an asymmetric two layer stepped QW channel sandwiched between two InAlAs barriers is proposed. A small bandgap InGaAs channel hosts the 2DEG-density and provides a low sheet resistance at low drain field. A higher bandgap sub channel of (a) InP and (b) InGaAs/InAlAs superlattice is designed to act as high field drift layer. This approach allows to obtain high f/sub maxf/sub t/-ratios and high output power at high speed. First results are given.<<ETX>>

Improved microwave performance of InP based HEMT using a floating gate tetrode arrangement

A novel floating gate tetrode device concept is presented and evaluated for high speed performance. In this structure the second gate is DC and RF unconnected and internally slightly positively self-biased. Even so, the second FET as well as the first FET need to be operated in saturation for optimum high gain performance. To obtain a lower output conductance and feedback capacitance, a deeper recess of the second gate in respect to the first gate is required. Then, under optimum bias conditions of gate 1, the channel current is reduced to approximately 0.4 of the maximum current and the f/sub max/ cut-off frequency is increased by a factor of 1.75 from f/sub max,triode/=205 GHz to f/sub max,FG-tetrode/=360 GHz. Due to the cascode circuit arrangement, the f/sub T/ is reduced from f/sub T,triode/=110 GHz to f/sub T,tetrode/=90 GHz. These numbers are obtained at a low drain bias of V/sub D/=1.2 V.

Microwave performance of InP-based HEMTs for low voltage application fabricated by optical lithography

The low voltage high frequency performance of InP-based HEMTs is examined. All the devices are fabricated by simple optical lithography resulting in gate length /spl ges/0.5 /spl mu/m. The RF results of the structures discussed show that uncompromised small RF performance of InP based FETs can be obtained in the low drain bias range below 2 V. Even for moderate gate lengths of 0.5 /spl mu/m, operation down to Vd=1 V seems feasible. The highest cut-off frequencies extrapolated are f/sub t/=60 GHz and f/sub max/=160 GHz at Vd=1.6 V. This represents an ft*Lg-product of 39 GHz/spl mu/m and a f/sub max//f/sub t/ of 2.6 at the identical gate and drain bias point. This indicates that high power gain is possible at high overshoot velocity. Three different material structures have been analysed. The drift-region analysis indicate that an optimum design is a structure with high open channel current density realised with high carrier concentration.

Optimized molecular beam epitaxial growth temperature profile for high-performance AlInAs/GaInAs single quantum well high electron mobility transistor structures

Abstract In molecular beam epitaxy (MBE) grown AlInAs/GaInAs single quantum well high electron mobility transistor structures, the use of low growth temperature for layers below the channel to suppress Si movement is mandatory. An optimized growth temperature profile has been elaborated as a prerequisite to reach high carrier concentrations in combination with high mobilities. The impact of an optimum growth temperature profile on device performance is demonstrated in devices with a saturation current of up to 1000 mA/mm.

RF-current de-confinement in III-V HFETs

A criterion for the carrier confinement in III-V HFETs is derived from the linear correlation between the two ratios Cgs/Cgd and gm/gds, where Cgs is the gate/source capacitance, Cgd is the gate/drain capacitance, gm is the transconductance, and gds is the output conductance. FETs of a number of distinctly different layer structures have been compared on this basis. The model finds carrier flow confinement dominated by the structural aspect ratio and the extension of the drain region. In the RF analysis no evidence for additional confinement of hot carriers by a deep-quantum-well channel configuration is found either in GaAs-based or in InP-based material systems.<<ETX>>