S. Summerfield

The design of wave digital filters using fully pipelined bit-level systolic arrays

Wave digital filters (WDF) based on analogue lattice and unit element cascade networks possess important properties that make them suitable for VLSI integration. These include low round-off noise even with short coefficient wordlength and a building block (two-port adaptor) with a very simple structure. Exploiting these properties leads to area efficient designs. Systolic architectures for these WDF networks give the additional advantage of very high sampling rates with potential application in sonar and video signal processing. The bit-level systolic array design of two WDFs is considered in detail, beginning at the filter specification and ending at the VLSI hardware architecture, with discussion of the expected values of the integrated circuit parameters.

A new pipelined architecture for allpass digital filters based on the 3-port adaptor

Allpass digital filters are major building blocks in many digital filter structures. A new pipelined architecture for the 2/sup nd/ order allpass section based on the 3-port series adaptor is presented. It is shown how to maximise the sample rate whilst applying the minimum level of pipelining. The new architecture has up to double the maximum sample rate of other structures.

Sigma-Delta bitstream filtering in VLSI

This paper considers the prospects for filters with analogue I/O and internal digital signal processing performed performed directly on a Sigma-Delta modulated bitstream, with potential applications to audio systems. Simulations verify equivalent 16-bit performance of a bitstream FIR filter. VLSI design is highly regular and initial evaluation indicates that bitstream filtering is a viable alternative to decimation followed by PCM filtering.

VLSI implementation of wave digital filters using systolic arrays

The authors previously investigated (in Systolic Array Processors, Prentice-Hall, 1989) the application of bit-level systolic arrays to the implementation of wave digital filters developed from cascades of unit elements. The method employed makes use of the characteristic short coefficient word-length property of wave digital filters. Here, they extend it to the case of the lattice wave digital filter (LTWDF). A practical filter design example is considered where a specification is met with 6-b coefficients, and a hardware model is developed for its implementation. Using transistor counts for area estimates, a VLSI floorplan is constructed and probable performance parameters are obtained. The authors find that the techniques are likely to yield area efficient devices capable of performing useful filtering operations at video signal frequencies.<<ETX>>

Novel pattern-based power estimation tool with accurate glitch modeling

In this paper an enhanced gate-level power estimation tool with efficient glitch modeling is presented. With little addition in computational cost from the traditional event driven simulation the new technique employs better delay modeling of glitch peaks through the introduction of glitch coefficients and appropriate glitch filtering to achieve improvement in accuracy. The simulator is shown to reduce the estimation error by up to 50% from the traditional toggle-based technique, and has accuracy within 10% of SPICE. The simulator post-processes Verilog-XL output and the overall run-time is better than SPICE by more than an order of magnitude.

VLSI arithmetic with current mode multiple valued logic

A general design methodology for arithmetic operators in current mode multiple value logic is described. It is based on the interconnection of single output functions of one current, quantizers, through summing nodes and current replicator circuits. Some quantizers are known already: radix 4 sum and carry circuits. The authors present new circuits for the discrete pseudologarithm and antilogarithm, which together give a single digit multiply circuit. These form a complete set that allows any arithmetic circuit to be constructed.<<ETX>>

A pipelining method for high speed VLSI wave digital filters

Wave Digital Filters are known to be superior in many respects to other IIR filter structures. The Lattice Wave Digital Filter, investigated here, is a highly efficient, modular structure that is suitable for VLSI implementation. Previous speed-critical design approaches have aimed at minimising the evaluation time of the single twoport adaptor, which is the repeated unit of the filter. However, more efficient designs can be obtained by concentrating on the pipelining techniques of the complete filter, and this is the approach applied here. This paper presents the derivation of a minimally pipelined Lattice Wave Digital Filter which leads to the structure with the highest sample rate given a specific coefficient wordlength and bit-level implementation technique.

Carry save and pipelining techniques for wave digital filters

Wave Digital Filters are known to be superior in many respects to other IIR filter structures and are suitable for high speed filtering applications. In this paper the two-port adaptor is used to implement both the Lattice and Bireciprocal Wave Digital Filters. The main computational element of the twoport adaptor and all other digital domain filters is the multiplier. Carry save techniques can efficiently implement the shift-and-add multiplication algorithm. Selection of which of the filter coefficient and data operands is the actual multiplier leads to the development of two arrays with different data flow characteristics. This paper compares and contrasts these two carry save arithmetic methodologies and applies them to the Bireciprocal and Lattice Wave Digital Filters. Emphasis will be placed on the usage of efficient pipelining schemes.<<ETX>>

Low latency architectures for wave digital filters

Wave digital filters constructed of networks of two port adaptors are candidates for VLSI implementation. Pipelining, and hence high data throughput, requires a low latency, high throughput, hardware structure for the two-port adaptor. This design problem is addressed in two main approaches, i.e., with systolic array techniques based on lsb first pipelining that exploit the low coefficient wordlength properties of wave digital filters, and with msb first pipelining based on signed digit number systems. These methods are extended, compared and contrasted; a new hardware scheme is presented; and it is indicated which arrangements are best suited for particular filtering applications.<<ETX>>

Area-power-time efficient pipeline-interleaved architectures for wave digital filters

Various forms of pipelining are explored for low power implementation of lattice wave digital filters realized with 3-port adaptors. In these filters, the time performance of pipelining is constrained by recursion. Using the fastest, block pipelined architecture as a reference point, it is shown that additional levels of pipelining can be applied to reduce the power consumption, at the expense of slightly changing the maximum sample rate. In one case power is reduced by 65% with only a modest speed penalty. Area increases due to additional pipeline registers can be more than offset if the consequent interleaving capability is utilized.