S. Voges

From wafer level to panel level mold embedding

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding technologies and embedding of active components into printed circuit boards (Chip-in-Polymer) are two major packaging trends in this area. Mold embedding is currently done on wafer level, typically with diameters of 8“ to 12”, for future process optimization, PCB technologies offer the potential of real large areas up to 610 × 457 mm2. For mold embedding as e.g. for fan-out wafer level packaging compression molding equipment is used in combination with liquid, granular or sheet epoxy molding compounds, with the boundary condition, that mold processes do need a product specific tool (with defined diameter & thickness). Within this paper the potential of tool-less lamination processes, a standard in PCB manufacturing, is evaluated. Lamination is done in panel format using well-known molding compounds from wafer level compression molding. To evaluate the potential of todays encapsulants for large area embedding processes, different liquid, granular and sheet molding compounds have been intensively evaluated on their processability, on process & material induced die shift and on resulting warpage - all on panel level. Acting as an interconnection layer, PCB based redistribution technologies using lamination of resin coated copper (RCC) films are used. Within the paper, different RCC materials are introduced and discussed concerning their reliability potential based on the available layer thicknesses and thermo-mechanical material properties. The feasibility of the proposed technologies is demonstrated using a two chip package. Dies are embedded in panel size by lamination technologies. Subsequently the wiring is done by lamination of an RCC film over the embedded components and on the panel backside for double sided redistribution. In a process flow also similar to conventional PCB manufacturing μvias to the die pads and through mold vias are drilled using a UV laser and are metalized by Cu-electroplating in one step. This way dies are connected to the front copper layer as well as front to backside of the panel. Conductor lines and pads are formed by Cu etching. Finally, a solder mask and a solderable surface finish are applied. If solder depots are necessary, e.g. for BGA packages, those can be applied by solder balling equipment - either by printing or by preform attach. In summary this paper describes the potential to move from wafer level to panel level mold embedding technology in combination with PCB based redistribution processes. The technology described offers a cost effective packaging solution for e.g. single chip packages as well as for future sensor/ASIC systems or processor/memory stacks in volume production.

Through mold via technology for multi-sensor stacking

With the increasing market of handheld electronics e.g. smartphones and tablet PCs also an increasing demand for highly miniaturized multi-sensor packages shows up. One application scenario here would be an electronic compass allowing indoor navigation in complex buildings with a smartphone. These applications of highly miniaturized heterogeneous system integration lead to a need for new packaging technologies which also allow large area processing and 3D integration with potential for low cost applications. Large area mold embedding is one major packaging trend in this area. This paper describes the use of advanced molding techniques for multi-chip embedding in combination with large area and low cost redistribution technology derived from printed circuit board manufacturing with focus on integration of through mold vias for package stacking. The use of compression molding equipment with liquid or granular epoxy molding compounds for the targeted integration process flow is a technological approach that has been developed to allow large area embedding of single chips but also of multiple chips or heterogeneous systems on wafer scale. Embedding area today is typically in the size range of 8” to 12” in diameter, while future developments will deal with panel sizes up to 470 × 370 mm². The wiring of the embedded components in this novel type of SiP is done using PCB manufacturing technologies, i.e. a resin coated copper (RCC) film is laminated over the embedded components — whichever no matter which shape they are: a compression molded wafer or a larger rectangular area or a Molded Array Package (MAP). Interconnects are formed by laser drilling to die pads and electroplating — all of them making use of standard PCB processes. Also through vias for z-axis interconnection, a standard features in PCB manufacturing, can be integrated in the proposed process flow for mold embedding in combination with RCC based redistribution. These vias were laser drilled after RCC lamination and were metalized together with the vias for chip interconnection. Reliability of the manufactured through mold vias with different via diameters and pitches was evaluated by moisture sensitivity level [MSL] testing, temperature cycling and humidity storage and test vehicles were analyzed both non-destructively and destructively. Results show high reliability potential of the introduced through mold via technology as samples have passed MSL 1 and more than 3000 temperature cycles and 3000 hour humidity storage without any electrical failure. The embedding and stacking technology is demonstrated for a functional two chip package consisting of an acceleration sensor and an ASIC. On top of this package a second wafer level embedded package is assembled containing a pressure sensor and an ASIC. Both WL packages are connected by the through mold vias and soldered to a base substrate. Concluding, within this paper on mold embedded SiPs both is shown — the development of TMVs, an advanced and low cost 3D packaging feature and demonstration of use of this feature for the assembly of a functional 3D multi-sensor system, illustrating the miniaturization potential of 3D system integration.

Fabrication of 3D Hybrid Pixel Detector Modules Based on TSV Processing and Advanced Flip Chip Assembly of Thin Read Out Chips

In this article we present the conception, technological fabrication and electrical characterization of 3D hybrid pixel detector modules based on read out chips (ROCs) with through silicon vias (TSVs) which are flip chip bonded onto silicon photon sensors for X-ray detection. The TSVs in the ROCs enable a vertical routing of their peripheral IOs to the back side where they are spread to a land grind array (LGA) with 800 µm pitch. Thus, the back side of the ROCs can be used for next level interconnection to LTCC system boards which allows a pure vertical system architecture. With this routing concept, area-consuming wire bond connections from the peripheral IOs of the ROCs to the system board can be avoided which is the base for edgeless detector configurations with a tiled assembly of ROCs without imaging dead zones. To enable the envisioned vertical system concept, the ROCs were post-processed with 100 µm deep copper filled TSVs, front and back side redistribution, micro solder bumps for connection to the detector and land grid array (LGA) for connection to the system board. The UFXC32k (Ultra Fast X-ray Chip with 32k channels) served as ROC device featuring an array of 32768 pixel IOs using a pitch of 75 mm, 87 peripheral chip IOs and a total size of 2 cm2. The sensor tiles were post-processed with copper pads to enable a side by side flip chip assembly of two ROCs onto each sensor. The LGAs on the back side of the ROCs were used to mount the sub-modules to the LTCC system boards, which were pre-assembled with SMDs and corresponding solder ball arrays. The fabricated 3D hybrid pixel modules show a good electrical performance and passed real X-ray imaging experiments. A high interconnect yield was achieved with only maximum 17 dead pixels out of 65536 total pixels per detector. These investigations took place in a joint project between Fraunhofer IZM in Berlin and AGH University of Science and Technology in Krakow.

Foldable Fan-Out Wafer Level Packaging

The constant drive to further miniaturization and heterogeneous system integration leads to a need for new packaging technologies that also allow large area processing and 3D integration with strong potential for low cost applications. Here, Fan-Out Wafer Level Packaging [FOWLP] is one of the latest packaging trends in microelectronics. For FOWLP known good bare dies are embedded into mold compound forming a reconfigured wafer. A redistribution layer is applied on the reconfigured wafer and routes the die pads to the space around and on the die. After bump formation and package singulation by dicing an SMD compatible package is completed. The technology can be also used for multi-chip packages or System in Package (SiP). 3D integration is typically done by package on package (PoP) stacking where the electrical 3D routing is done by through mold vias or vertical interconnect elements [VIE] and a redistribution layer on both sides of the FOWLP. A Foldable Fan-out Wafer Level Package (FFOWLP) would now allow a single sided planar processing and yield a stacked three dimensional package by folding only. Folding can be implemented by a combination of a flexible redistribution layer and a dicing process that only cuts through the molding compound but leaves the redistribution layer untouched. As foldable redistribution layer e.g. polyimide can be used, a standard for flexible substrates. The feasibility of the proposed technology is demonstrated using a multi-chip package. Dies are mold embedded in wafer size. Subsequently the wiring is done by lamination of a polyimide film over the embedded components. In a process flow similar to conventional PCB manufacturing μvias are drilled to the die pads using a UV laser and metalized by Cu-electroplating. Conductor lines and pads are formed by Cu etching. A solder mask can be applied for pad definition. Finally, the wafer will be diced in two steps. First the bending cuts will be done by dicing only through the molding compound and in a second step package singulation will be carried out. Besides folding for package stacking the technology can be also be used to integrate multi-die packages into free form factor surfaces as bows, curves or defined angles. Upscaling of the technology described above from wafer to panel is also possible and offers low cost solutions and large/long foldable FOWLP stripes in a well-defined package.

Panel level packaging for LED lighting

General lighting by use of LED-Chips is one of the strongly growing markets today and also in future. One of the trends goes to LEDs with higher and higher luminous fluxes per chip area to get the best price per lumen on the market. Unfortunately, such large LEDs produce a lot of heat, which must be spread to avoid overheating and shorter lifetime of the LEDs. Another approach is the use of many small LEDs so that both light and heat source are spread into a larger area. Cost-effective established PCB-technology was applied to produce large-area light sources consisting of many small LED chips placed and electrically connected on a PCB-substrate. LEDs were ICA-bonded with their bottom pad to the PCB. The top contacts of the LEDs were established by laminating an adhesive copper sheet followed by a LDI structuring as known from PCB-via-technology. This assembly can then be completed by adding converting and light forming optical elements.

Challenges and opportunities for Fan-out Panel Level Packing (FOPLP)

Fan-out Wafer Level Packaging (FOWLP) is one of the latest packaging trends in microelectronics. Mold embedding for this technology is currently done on wafer level up to 12”/300 mm size. For higher productivity and therewith lower costs larger mold embedding form factors are forecasted for the near future. Following the wafer level approach then the next step will be a reconfigured wafer size of 450 mm. An alternative option would be leaving the wafer shape and moving to panel sizes leading to Fan-out Panel Level Packaging (FOPLP). Sizes for the panel could range up to 18”×24” or even larger. For reconfigured mold embedding, compression mold processes are used in combination with liquid, granular or sheet compound. As an alternative process, lamination can be also considered. Already today PCB technologies offer the potential for large area panel packaging up to 24”×18”/610 × 457 mm2 and can be applied to form a redistribution layer [RDL] for large area reconfigured wafers or panels, replacing thin film redistribution. For PCB based RDLs a resin coated copper sheet (RCC) is laminated on the reconfigured wafer or panel, respectively. Micro vias are drilled through the RCC layer to the die pads and electrically connected by Cu plating. Final process step is the etching of Cu lines using LDI techniques for maskless patterning. State of the art equipment and materials the manufacturing of structures down to 20 μm lines and spaces with a clear development trend to 10 μm lines and spaces and hence getting close to photolithography thin film structure sizes. Using the above mentioned maskless laser direct imaging technologies (LDI) instead of photolithography have a high potential for further cost reduction with intrinsic process advantages. The LDI cost advantage is backed by LDI availability for large panel sizes, also including 450 mm wafer form factors. Based on the technology described the Fan-out Panel Level Packaging approach will be demonstrated on full 24”×18”/610 × 457 mm2 format including large area assembly, embedding and redistribution. Related technology challenges as die shift, warpage, panel handling or yield will be discussed in detail. Using maskless LDI technology real die positions could be automatically adapted to the redistribution and hence less accurate die placement can be compensated and higher die shift could be tolerated which is a big advantage when moving towards large area with acceptable yield. In summary this paper describes the technological path from wafer level embedding to 24”×18” fan-out panel level packaging technology in combination with low cost PCB based RDL processes and discusses challenges and opportunities in detail. The technology described offers a cost effective packaging solution for various application as packages for handheld consumer application or bio-medical application as sensor integration into microfluidics.