Sabooh Ajaz

Hand gesture tracking and recognition system using Lucas-Kanade algorithms for control of consumer electronics

Abstract Dynamic hand gesture tracking and recognition system can simplify the way humans interact with computers and many other non-critical consumer electronic equipments. This system is based on the well-known “Wave Controller” technology developed at the University of Wollongong [1] , [2] , [3] and certainly a step forward in video gaming and consumer electronics control interfaces. Currently, computer interfacing mainly involves keyboard, mouse, joystick or gaming wheels and occasionally voice recognition for user input. These modes of interaction have constrained the artistic ability of many users, as they are required to respond to the computer through pressing buttons or moving other apparatus. Voice recognition is seen as unreliable and impractical in areas where more than one user is present. All these drawbacks can be tackled by using a reliable hand gesture tracking and recognition system based on both Lucas–Kanade and Moment Invariants approaches. This will facilitate interaction between users and computers and other consumer electronic equipments in real time. This will further enhance the user experience as users are no longer have any physical connection to the equipment being controlled. In this research, we have compared our proposed moment invariant based algorithm with template based and Fourier descriptor based methods to highlight the advantages and limitations of the proposed system.

High-Throughput Low-Complexity Successive-Cancellation Polar Decoder Architecture using One’s Complement Scheme

This paper presents a high-throughput lowcomplexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one’s complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two’s complement scheme in merged processing elements, in which a conversion between two’s complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

Efficient Min-Max nonbinary LDPC decoding on GPU

This paper presents an novel modified Min-Max algorithm (MMMA) and an efficient implementation of an nonbinary LDPC (NB-LDPC) decoder on a graphics processing unit (GPU) to achieve both great flexibility and scalability. The MMMA for check node processing removes the multiplications over Galois-field in merger step and significantly reduces the decoding latency. The proposed MMMA provides a better BER performance than previous algorithm. The experimental results show that the GPU-based implementation of the proposed NB-LDPC decoder provides higher throughput and the coding gain under low 10-8 BER comparted to CPU-based implementation.

Multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad standard

This paper presents an area-efficient multi-Gbps multi-mode LDPC decoder architecture for 60GHz wireless gigabit communications. A novel, low-complexity local switch is proposed to implement the multi-mode dynamic column-shifting scheme. Furthermore, the usage of a ones-complement instead of a twos-complement number system is explored. Moreover, an efficient quantization method is also presented to reduce the memory and area requirement of the decoder. The synthesis and layout is performed using TSMC 65-nm CMOS technology. Post layout results show that the proposed decoder requires only 0.575 mm2 of area to achieve a throughput of 9.25 Gb/s for all code rates defined under IEEE 802.11ad. The proposed architecture shows much better throughput, as well as better area- and energy-efficiency, compared to other multi-mode LDPC architectures.

Parallel block-layered nonbinary QC-LDPC decoding on GPU

This paper presents an efficient implementation of a parallel block-layered nonbinary quasi-cyclic low-density parity-check (NB-QC-LDPC) decoder on a graphics processing unit (GPU) to achieve significant improvements in both flexibility and scalability. An efficient block-layered scheme and a data structure suitable for parallel computing are proposed to perform decoding on the GPU. The scheme is applied to a min-max decoding algorithm that exploits the inherent massive parallelization capabilities of NB-QC-LDPC decoder. The results of the proposed approach demonstrate that the layered scheme can be efficiently implemented in a GPU device. Moreover, experimental results show that the proposed GPU-based block-layered NB-QC-LDPC decoder provides a faster decoding runtime compare to CPU-based implementation and obtains a coding gain under a low 10-10 BER and low 10-7 FER.

Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications

This paper presents a novel multi-Gb/s multi-mode LDPC decoder architecture and efficient design techniques for gigabit wireless communications. An efficient dynamic and fixed column-shifting scheme is presented for multi-mode architectures. A novel low-complexity local switch is proposed to implement the dynamic and fixed column-shifting scheme. Furthermore, an efficient quantization method and the usage of a ones-complement scheme instead of a twos-complement scheme are explored. The proposed decoder achieves very high throughput with minimal area overhead. Post layout results using TSMC 65-nm CMOS technology shows much better throughput, as well as better area- and energy-efficiency, compared to other multi-mode LDPC decoders. The usage of ones complement instead of conventional twos complement number system is explored. Ones complement provides a reduction in critical path and hardware complexity. A dynamic column shifting scheme for a pipelined multi-mode decoder is presented. The proposed scheme enables multi-mode operation with the minimal increase in the decoder area. A very low complexity local switch is presented to implement the proposed dynamic column shifting scheme.The proposed decoder occupies only 0.575 mm2 of core area using 65-nm CMOS technology. In addition, it achieves a throughput of 9.25 Gb/s at 400 MHz for all modes. In terms of throughput, hardware complexity, energy efficiency and area efficiency, the proposed multi-mode LDPC decoder is superior to the previous works.

An efficient radix-4 Quasi-cyclic shift network for QC-LDPC decoders

A Radix-4 Quasi-cyclic shift network (QSN) for reconfigurable QC-LDPC decoders is presented in this paper. A complexity reduction technique is described to reduce the total gate count at each stage in addition to the fact that Radix-4 logarithmic barrel shifter naturally offers less number of stages compared to Radix-2. The proposed Radix-4 QSN architecture supports various code rates and all sizes of sub matrices. Moreover, a novel Radix-4 signal generator is proposed which is particularly an essential element for reconfigurable LDPC decoders. The synthesis, placement and routing (P & R) of the proposed network is performed using TSMC 90-nm standard cell CMOS technology. The implementation results shows that the proposed network outperforms its predecessors by about 11% and 38% in terms of area and clock frequency respectively.

Area efficient half row pipelined layered LDPC decoder for gigabit wireless communications

This work presents an area efficient half row partially parallel pipelined LDPC decoder architecture for IEEE 802.11ad standard. It provides better area and throughput tradeoff by overcoming the low throughput bottleneck in conventional half row decoders and high complexity bottleneck in fully parallel decoders. The proposed architecture is implemented using 40-nm CMOS technology. The proposed half-row pipelined decoder achieves the maximum required throughput of 8.4 Gb/s for IEEE 802.11ad standard and shows superior area efficiency compared to previous works.