Saeed Golestan

Three-Phase PLLs: A Review of Recent Advances

A phase-locked loop (PLL) is a nonlinear negative-feedback control system that synchronizes its output in frequency as well as in phase with its input. PLLs are now widely used for the synchronization of power-electronics-based converters and also for monitoring and control purposes in different engineering fields. In recent years, there have been many attempts to design more advanced PLLs for three-phase applications. The aim of this paper is to provide overviews of these attempts, which can be very useful for engineers and academic researchers.

PLL With MAF-Based Prefiltering Stage: Small-Signal Modeling and Performance Enhancement

In three-phase applications, the synchronous reference frame phase-locked loop (SRF-PLL) is a standard PLL, which benefits from a simple structure and satisfactory performance under symmetrical and undistorted grid conditions. Under unbalanced and harmonically distorted conditions, however, it suffers from a very poor performance in the detection of grid voltage parameters. To deal with this challenge, incorporating different filters inside its control loop or before its input has been proposed. Recently, using the moving average filter (MAF) as the SRF-PLL prefiltering stage has been suggested in several works. The MAF is a linear-phase filter that can behave like an ideal low-pass filter under certain conditions. The main aim of this letter is to derive the small-signal model of the SRF-PLL with MAF-based prefiltering stage (briefly called the PMAF-PLL), which has not been presented before. This model enables the designer to simply analyze the stability condition and dynamic behavior of the PMAF-PLL. After developing the model, a simple yet effective modification to enhance the PMAF-PLL performance under frequency varying environments is presented. Finally, the equivalence of the PMAF-PLL and the space-vector Fourier transform-based PLL (SVFT-PLL), which is a well-known PLL in the three-phase applications, is proved. This equivalence implies that the small-signal model of the PMAF-PLL and the method presented to enhance its performance are valid for the SVFT-PLL.

Small-Signal Modeling, Stability Analysis and Design Optimization of Single-Phase Delay-Based PLLs

Generally speaking, designing single-phase phaselocked loops (PLLs) is more complicated than three-phase ones, as their implementation often involves the generation of a fictitious orthogonal signal for the frame transformation. In recent years, many approaches to generate the orthogonal signal have been proposed, the simplest perhaps being the transfer delay-based method. In the transfer delay-based PLL (TD-PLL), the orthogonal signal is generated by delaying the original single-phase signal by T/4 (one-quarter of a period). The phase shift caused by the transfer delay block, however, will not be exactly 90° under off-nominal grid frequencies, which results in errors in the estimated quantities by the TD-PLL. To alleviate this issue, an improved version of TD-PLL, called the nonfrequency-dependent TD-PLL (NTD-PLL), has recently been proposed. The NTD-PLL uses another T/4 delay unit in its feedback path to make the PLL immune to grid frequency variations. To the best of the authors knowledge, the accurate small-signal modeling of the TD-PLL and NTD-PLL has not yet been carried out, and no detailed analysis of their performance has been presented. The main aim of this paper is to address these issues and explore new methods to enhance their performance. The stability analysis, control design guidelines, and performance comparison with the state-of-the-art PLLs are presented as well.

Inducverters: PLL-Less Converters With Auto-Synchronization and Emulated Inertia Capability

Inspired by induction machines working principles, this paper presents the idea of phase-locked-loop-less (PLL-less) operation of grid-connected voltage source converters (VSCs) under new concept of inducverter. The proposed controller eliminates the need for a dedicated synchronization process and the related PLL, and therefore it offers a simpler and more reliable control strategy compared to the conventional methods. In addition, it represents an improved performance, as it provides real and true auto-start and auto-synchronization with a grid without the need for grid voltage information. A current damping/synchronization unit enables grid auto-synchronization by using local current information and can track grid voltage frequency, angle, and amplitude variations while feeding constant amount of power, which is of high-interest in frequency varying grids and also in the case of grid voltage angle jump. Another advantage of the inducverter is that it introduces virtual inertia to the grid to regulate frequency, which enhances frequency dynamics of smart grids. Beside the current synchronization unit, the proposed strategy has a single-loop controller core with control over both power and current, which is implemented in a hybrid dq and abc frame using a virtual adaptive lead or lag impedance. The controller also offers stable and high-performance synchronization and operation under unbalanced and/or distorted grid conditions. The work beside synchronous current converters gives a birds eye view to research in the new area of PLL-less and virtual inertia-based operation of VSCs and fulfill a unified set of controllers for the smart grid integration. Simulation, hardware-in-loop, and experimental results are presented to validate effectiveness of the controller.

Single-Phase PLLs: A Review of Recent Advances

Single-phase phase-locked loops (PLLs) are popular for the synchronization and control of single-phase grid-connected converters. They are also widely used for monitoring and diagnostic purposes in the power and energy areas. In recent years, a large number of single-phase PLLs with different structures and properties have been proposed in the literature. The main aim of this paper is to provide a review of these PLLs. To this end, the single-phase PLLs are first classified into two major categories: 1) power-based PLLs and 2) quadrature signal generation-based PLLs. The members of each category are then described and their pros and cons are discussed. This paper provides a deep insight into characteristics of different single-phase PLLs, and therefore, can be considered as a reference for researchers and engineers.

DC-Offset Rejection in Phase-Locked Loops: A Novel Approach

Phase-locked loops (PLLs) are undoubtedly the most popular synchronization technique in the power and energy applications. A challenging problem of designing PLLs is the presence of dc offset in their input, which causes fundamental-frequency oscillatory errors in their estimated quantities. In this paper, a novel method to tackle this problem is presented. The effectiveness of this approach is verified through numerical results.

Hybrid Adaptive/Nonadaptive Delayed Signal Cancellation-Based Phase-Locked Loop

To improve the disturbance rejection capability of phase-locked loops (PLLs), which are undoubtedly the most common synchronization tool in power and energy applications, using different filtering techniques have been suggested in the literature. Among these filtering strategies, the delayed signal cancellation (DSC) operator is highly popular probably because it can be easily tailored for different grid scenarios. The DSC operator(s) can be used either as an in-loop filter in the PLL structure or as a preprocessing filter before the PLL input. The latter case is often preferred mainly because it results in a faster dynamic response in the extraction of grid voltage parameters. In this paper, a combination of an adaptive DSC operator with multiple nonadaptive DSC operators is suggested as the PLL preprocessing stage. To compensate for the phase and amplitude errors caused by the nonadaptive operators, a compensator is designed and cascaded with them. The proposed filter requires a low computational burden for the implementation and ensures a fast dynamic response and high filtering capability for the PLL. The effectiveness of this technique is verified through experimental results.

An Adaptive Quadrature Signal Generation-Based Single-Phase Phase-Locked Loop for Grid-Connected Applications

The quadrature signal generation-based phase-locked loops (QSG-PLLs) are highly popular for synchronization purposes in single-phase systems. The main difference among these PLLs often lies in the technique they use for creating the fictitious quadrature signal. One of the most popular QSG approaches is delaying the original single-phase signal by a quarter of a cycle. The PLL with such QSG technique is often called the transfer delay-based PLL (TD-PLL). The TD-PLL benefits from a simple structure, rather fast dynamic response, and a good detection accuracy when the grid frequency is at its nominal value, but it suffers from a phase offset error and double-frequency oscillatory error in the estimated quantities in the presence of frequency drifts. In this paper, a simple yet effective approach to remove the aforementioned errors of the TD-PLL is proposed. The resultant PLL structure is called the adaptive TD-PLL (ATD-PLL). The stability of the ATD-PLL is evaluated by the derivation of its small-signal model. Parameter design guidelines are also presented. Finally, the effectiveness of the ATD-PLL is confirmed using numerical results.

An Adaptive Least-Error Squares Filter-Based Phase-Locked Loop for Synchronization and Signal Decomposition Purposes

Without any doubt, phase-locked loops (PLLs) are the most popular and widely used technique for the synchronization purposes in the power and energy areas. They are also popular for the selective extraction of fundamental and harmonic/disturbance components of the grid voltage and current. Like most of the control algorithms, designing PLLs involves a tradeoff between the accuracy and dynamic response, and improving this tradeoff is what recent research efforts have focused on. These efforts are often based on designing advanced filters and using them as a preprocessing tool before the PLL input. A filtering technique that has received a little attention for this purpose is the least-error squares (LES)-based filter. In this paper, an adaptive LES filter-based PLL, briefly called the LES-PLL, for the synchronization and signal decomposition purposes is presented. The proposed LES filter can be understood as an adaptive complex-coefficient filter because its implementation involves cross couplings between orthogonal axes. The stability of designed LES-PLL is analyzed by the derivation of its small-signal model. Some control design guidelines are also presented. The effectiveness of proposed PLL structure is finally evaluated using experimental results.

A True Open-Loop Synchronization Technique

Synchronization techniques can be broadly classified into two major categories-closed-loop and open-loop methods. The open-loop synchronization (OLS) techniques, contrary to the closed-loop ones, are unconditionally stable and benefit from a fast dynamic response. Their performance, however, tends to worsen in the presence of frequency drifts. To deal with this problem, two approaches are often recommended in the literature-adapting OLS techniques to the grid frequency variations by feeding back the frequency estimated by them or using the frequency estimated by a secondary frequency detector in a parallel manner. In the presence of the frequency feedback loop, nevertheless, the OLS technique may not be truly open-loop, which makes a deep stability analysis necessary. Using the secondary frequency detector, on the other hand, increases the computational effort and implementation complexity. Another drawback of most of the available OLS techniques is that their implementation involves the computation of sine and cosine functions, which is undesirable from the computational standpoint, particularly when the implementation with low-cost digital signal processors is intended. The aim of this paper is to develop a true OLS (and therefore, unconditionally stable) technique without any need for the calculation of sine and cosine functions. The effectiveness of the proposed synchronization technique is confirmed through the simulation and experimental results.