Safar Hatami

A Novel Architecture of Delta-Sigma Modulator Enabling All-Digital Multiband Multistandard RF Transmitters Design

This paper proposes a new architecture of delta-sigma (DS) modulator suitable for RF digital transmitter design. This novel architecture considerably reduces the speed requirements of the digital signal processing block. The novelty lies in the implementation of a specific fully digital up-conversion in combination with a low-pass DS modulator to produce high-frequency digital-like signals, which can be used to drive highly efficient switching-mode power amplifiers. The proposed architecture is suitable for reconfigurable all-digital, multistandard and multiband wireless transmitters. The novel transmitter architecture has been validated using simulation and implemented on a field-programmable gate array development board for two different signals, code division multiple access and orthogonal frequency division multiplex.

Minimizing the Electricity Bill of Cooperative Users under a Quasi-Dynamic Pricing Model

Dynamic energy pricing is a promising development that addresses the concern of finding an environmentally friendly solution to meeting energy needs of customers while minimizing their electrical energy bill. In this paper, we mathematically formulate the electrical energy bill minimization problem for cooperative networked consumers who have a single energy bill, such as those working in a commercial/industrial building. The idea is to schedule user requests for appliance use at different times during a fixed interval based on dynamic energy prices during that interval. Two different methods are presented to minimize the energy cost of such users under non-interruptible or interruptible jobs. The methods relay on a quasi-dynamic pricing function for unit of energy consumed, which comprises of a base price and a penalty term. The methods minimize the energy cost of the users while meeting all the scheduling constraints and heeding the pricing function. The proposed methods result in significant savings in the energy bill under different usage pricing, and scheduling constraints.

Demand-side load scheduling incentivized by dynamic energy prices

Demand response is an important part of the smart grid technologies. This is a particularly interesting problem with the availability of dynamic energy pricing models. Electricity consumers are encouraged to consume electricity more prudently in order to minimize their electric bill, which is in turn calculated based on dynamic energy prices. In this paper, task scheduling policies that help consumers minimize their electrical energy cost by setting the time of use (TOU) of energy in the facility. Moreover, the utility companies can reasonably expect that their customers reduce their consumption at critical times in response to higher energy prices during those times. These policies target two different scenarios: (i) scheduling with a TOU-dependent energy pricing function subject to a constraint on total power consumption; and (ii) scheduling with a TOU and total power consumption-dependent pricing function for electricity consumption. Exact solutions (based on Branch and Bound) are presented for these task scheduling problems. In addition, a rank-based heuristic and a force directed-based heuristic are presented to efficiently solve the aforesaid problems. The proposed heuristic solutions are demonstrated to have very high quality and competitive performance compared to the exact solutions. Moreover, ability of demand shaping utilizing the aforementioned pricing schemes is demonstrated by the simulation results.

Accurate Power Efficiency Estimation of GHz Wireless Delta-Sigma Transmitters for Different Classes of Switching Mode Power Amplifiers

This paper proposes a new closed-form expression for computing the power efficiency of delta-sigma (DS) radio frequency (RF) transmitters. Due to the large bandwidth of the pulsewidth modulated (PWM) signal at the output of the DS modulator, the peak efficiency of the power amplifier (PA) when driven by a PWM signal is considerably different than its peak efficiency when the input signal is a continuous sine wave. A weight averaging of the efficiency over the frequency bandwidth of the PWM signal is considered for accurate estimation and prediction of the power efficiency of DS RF transmitters. It is shown that, for a low-pass DS transmitter, the overall average power efficiency of the DS transmitter can be accurately estimated by the product of the modulated peak efficiency of the PA and the coding efficiency of the modulator. For bandpass DS transmitters, an additional parameter that accounts for the duty cycle effect on the efficiency of switching-mode PAs has to be considered. To validate the new proposed expression, a DS transmitter for WiMAX, CDMA and EDGE standards is designed, prototyped and tested. The comparison of the simulated and measured efficiencies of the DS transmitter proves the validity and accuracy of the proposed expression.

NBTI-aware flip-flop characterization and design

With the scaling down of the CMOS technologies, Negative Bias Temperature Instability (NBTI) has become a major concern due to its impact on PMOS transistor aging process and the corresponding reduction in the long-term reliability of CMOS circuits. This paper investigates the effect of NBTI phenomenon on the setup and hold times of flip-flops. First, it is shown that NBTI tightens the setup and hold timing constraints imposed on the flip-flops in the design. Second, different types of flip-flops exhibit different levels of susceptibility to NBTI-induced change in their setup/hold time values. Finally, an NBTI-aware transistor sizing technique can minimize the NBTI effect on timing characteristics of the flip-flops.

Concurrent optimization of consumer's electrical energy bill and producer's power generation cost under a dynamic pricing model

Demand response is a key element of the smart grid technologies. This is a particularly interesting problem with the use of dynamic energy pricing schemes which incentivize electricity consumers to consume electricity more prudently in order to minimize their electric bill. On the other hand optimizing the number and production time of power generation facilities is a key challenge. In this paper, three models are presented for consumers, utility companies, and a third-part arbiter to optimize the cost to the parties individually and in combination. Our models have high quality and exhibit superior performance, by realistic consideration of non-cooperative energy buyers and sellers and getting real-time feedback from their interactions. Simulation results show that the energy consumption distribution becomes very stable during the day utilizing our models, while consumers and utility companies pay lower cost.

A current source model for CMOS logic cells considering multiple input switching and stack effect

This paper presents a current source model (CSM) of a CMOS logic cell, which captures simultaneous switching of multiple inputs while accounting for the effect of internal node voltages of the logic cell. Characterization procedures for various components of the proposed CSM are described and application of the model to output waveform computation is discussed. Experimental results to assess the accuracy and efficiency of the proposed multiple input switching CSM in the context of noise and timing analyses in VLSI circuits are reported.

Statistical timing analysis of flip-flops considering codependent setup and hold times

Statistical static timing analysis (SSTA) plays a key role in determining performance of the VLSI circuits implemented in state-of-the-art CMOS technology. A pre-requisite for employing SSTA is the characterization of the setup and hold times of the latches and flip-flops in the cell library. This paper presents a methodology to exploit the statistical codependence of the setup and hold times. The approach comprises of three steps. In the first step, probability mass function (pmf) of codependent setup and hold time (CSHT) contours are approximated with piecewise linear curves by considering the probability density functions of sources of variability. In the second step, pmf of the required setup and hold times for each flip-flop in the design are computed. Finally, these pmf values are used to compute the probability of individual flip-flops in the design passing the timing constraints and to report the overall pass probability of the flip-flops in the design as a histogram. We applied the proposed method to true single phase clocking flip-flops to generate the piecewise linear curves for CSHT. The characterized flip-flops were instantiated in an example design, on which timing verification was successfully performed.

Multi-objective optimization techniques for VLSI circuits

The EDA design flows must be retooled to cope with the rapid increase in the number of operational modes and process corners for a VLSI circuit, which in turn results in different and sometimes conflicting design goals and requirements. Single-objective solutions to various design optimization problems, ranging from sizing and fanout optimization to technology mapping and cell placement, must hence be augmented to deal with this changing landscape. This paper starts off by presenting a variety of methods for providing analytical models for power and delay to be used in the optimization algorithms. The modeling includes non-convex and convex functional forms. Next, a class of robust and scalable methods for solving multi-objective optimization problems (MOP) in a digital circuit is presented. We present the results of a multi-objective (i.e., power dissipation and delay) gate (transistor) sizing optimization algorithm to demonstrate the effectiveness of our method. We set up the problem as a simultaneous, multi-objective optimization problem and solve it by using the Weighted Sum and Compromise Programming methods. After comparing these two methods, we present the Satisficing Trade-off Method (STOM) to find the most desirable operating point of a circuit.

Wavelet based fingerprint image enhancement

Fingerprint image enhancement is aimed at improving the quality of local features for automatic fingerprint identification. It will allow accurate feature extraction and identification. In this paper, we have considered the use of wavelets for fingerprint enhancement mainly due to their spatial localization property as well as capability to use oriented wavelets such as Gabor wavelets for orientation flow estimation. The proposed algorithm consists of two-stage processing: smoothing and Gabor wavelet filtering. Our smoothing part of enhancement algorithm reduces the noise by a new technique based on Gaussian filtering. Since Gaussian filters meet the uncertainty principle at its limits, they are considered here as the best choice for smoothing and noise reduction. The Gabor wavelet is applied to improve the quality of the smoothed image. Gabor filters are commonly used for enhancement in which the frequency and orientation estimation is required for the enhancement. However, the proposed algorithm is independent of the estimation part. Simulation results are included illustrating the capability of the proposed algorithm.